F.G. Kuper

Data retention prediction for modern floating gate non-volatile memories

Abstract Extensive gate stress measurements after cycling on test structures and on products have been carried out on EEPROMS. The leakage current in the worst case SILC cell has been measured at very low electrical field (down to 1 MV/cm), and has been fitted with various formulae like Fowler-Nordheim (FN), Poole-Frenkel (PF), trap-assisted tunneling (TAT) and hopping conduction model (HCM). In such EEPROMS, a strong asymmetry of SILC has been found. The SILC at low-Vt state is worse than that at high-Vt state. The effect of pulse shaping on suppressing SILC is also demonstrated. A new method is reported to perform data retention estimation and product reliability based on field accelerated tests (gate stress tests). The data retention time of the SILC cell has been determined based on the worst case data from gate stress experiments. The new method can be applied to other floating gate non-volatile memories, such as flash.

Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate reduction programs

The relation between yield and early failures as encountered in the field was investigated with several high volume ICs manufactured in several processes. A clear correlation between yield and reliability was found that obeys a simple model. The model also provides the ability to predict the FIT or PPM level of a given IC based on its yield. Using these results we illustrate how a wafer fab may improve the reliability level of its products in a controlled way.

The effect of silicide on ESD performance

In this paper, a new model for localized breakdown in grounded gate NMOSTs under ESD stress is developed which accounts for the reduced ESD strength in silicided devices. The model explains the impact of a stabilizing drain resistance on second breakdown current for both silicided and unsilicided ESD protection NMOSTs.

Impact of screening of latent defects at electrical test on the yield-reliability relation and application to burn-in elimination

This paper addresses the question of under what conditions burn-in can be eliminated. Based on data of more than 30 million sold devices, the effect of screening of latent defects at electrical test on product reliability has been investigated. The results are combined with the yield-reliability relation and an experimentally determined failure rate time evolution, yielding a model that allows determination of the sense or nonsense of burn-in or screens at electrical test quantitatively. The model predictions are in good agreement with experimental data. Furthermore, for typical operating conditions, high yielding batches show a better long term reliability than low yielding batches even if the latter have been subjected to burn-in. It is also shown that voltage stresses, distribution tests and IDDQ screens can be good alternatives to burn-in.

MOSFET Degradation Under RF Stress

We report on the degradation of MOS transistors under RF stress. Hot-carrier degradation, negative-bias temperature instability, and gate dielectric breakdown are investigated. The findings are compared to established voltage- and field-driven models. The experimental results indicate that the existing models are well applicable into the gigahertz range to describe the degradation of MOS transistors in an RF circuit. The probability of gate dielectric breakdown appears to reduce rapidly at such high stress frequencies, increasing the design margin for RF power circuits.

Grounded-gate nMOS transistor behavior under CDM ESD stress conditions

This paper contains a systematic study into the effects of design and process variations on the behavior of the grounded-gate nMOS transistor under CDM ESD stress conditions. The correlation of both electrical behavior and physical failure is evaluated for socketed CDM, nonsocketed CDM, and HBM ESD stress models. It is shown that a new compact transistor model, concerning its application for the simulation of CDM behavior, is employed in electro-thermal simulation to explain the experimental results.

A concept to relate wire bonding parameters to bondability and ball bond reliability

Abstract The effects of wire bonding parameters on bondability and ball bond reliability have been investigated. Bondability is characterized by ball shear stress (ball shear force per unit area) and ball bond reliability by median time to failure during in-situ ball bond degradation measurements. By introducing the concept of a reduced bonding parameter (RBP), a combination of all bonding parameters, we are able to relate the bonding parameters to bondability and ball bond reliability. With the appropriate RBP, ball shear force, ball shear stress, andball bond reliability appear to be well-behaved functions of the RBP fora wide range of settings. This provides us with simple analytical tool for optimizing bonding parameter windows.

Effect of thermal gradients on the electromigration life-time in power electronics

The combined effects of electromigration and thermomigration are studied. Significantly shorter electromigration lifetimes are observed in the presence of a temperature gradient. This cannot be explained by thermomigration only, but is attributed to the effect of temperature gradient on electromigration-induced failures.

Automotive IC reliability : Elements of the battle towards zero defects

The battle towards zero defects consists of fast response to PPM signals, prevention of incidents and continuous improvement. In this paper elements of all three branches are treated. A PPM analysis tool called quality crawl charts is introduced that enables prediction of customer complaint levels based on an early set of warranty call rate data. The fact that the automotive industry is very cautious with process and product changes can be better understood better with a given practical example of a small change with (in the eyes of automotive) big consequences. Finally it is shown that continuous PPM reduction activities also have an effect on the number of EOS/ESD customer returns, and that this category of fails form a shared responsibility for both supplier and customer.

Fast temperature cycling and electromigration induced thin film cracking multilevel interconnection: experiments and modeling

There is an increasing reliability concern of thermal stress-induced and electromigration-induced failures in multilevel interconnections in recent years. This paper reports our investigations of thinfilm cracking of a multilevel interconnect due to fast temperature cycling and electromigration stresses. The fast temperature cycling tests have been performed in three temperature cycle ranges. The failure times aare represented well by a Weibull distribution. The distributions are relatively well behaved with generally similar slope (shape factor). The failure mechanism is well fitted by the Coffin-Manson equation indicating a uniform acceleration. The observation of cracking in the interlayre dielectric due to fast temperature cycling stress from failure analysis agrees well with the failure mechanism modeling and the calculated Coffin-Manson exponent. Electromigration experiments have shown that devices failed due to extrusion-shorts without increasing of resistance of metal line. The failure times are represented better by the Weibull distribution than by the lognormal distribution (normally used for electromigration data). A simulation of stress buil-up in metal line using an electromigration simulator confirmed that the cracking of interlayer dielectric is the weakest spot and most likely to cause electromigration failure.