A.J. Mouthaan

Fast temperature cycling and electromigration induced thin film cracking multilevel interconnection: experiments and modeling

There is an increasing reliability concern of thermal stress-induced and electromigration-induced failures in multilevel interconnections in recent years. This paper reports our investigations of thinfilm cracking of a multilevel interconnect due to fast temperature cycling and electromigration stresses. The fast temperature cycling tests have been performed in three temperature cycle ranges. The failure times aare represented well by a Weibull distribution. The distributions are relatively well behaved with generally similar slope (shape factor). The failure mechanism is well fitted by the Coffin-Manson equation indicating a uniform acceleration. The observation of cracking in the interlayre dielectric due to fast temperature cycling stress from failure analysis agrees well with the failure mechanism modeling and the calculated Coffin-Manson exponent. Electromigration experiments have shown that devices failed due to extrusion-shorts without increasing of resistance of metal line. The failure times are represented better by the Weibull distribution than by the lognormal distribution (normally used for electromigration data). A simulation of stress buil-up in metal line using an electromigration simulator confirmed that the cracking of interlayer dielectric is the weakest spot and most likely to cause electromigration failure.

Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations

Circuit aging simulation is seen as a true enhancement to device and circuit simulation. To predict aging of circuit performance, tested models for device parameters are needed in which the change in device behavior as function of time, given the biasing and temperature condition of the device in the circuit, is correctly modeled. The time scale here is the lifetime of the product. A circuit simulator in the transient mode can predict circuit aging using a transformation of the dc/ac biasing situation with an appropriate scaling mechanism. Device aging models that can be implemented in such a circuit simulator are presented here for nMOS and DMOS (double diAused MOS) based on measurements and empirical modeling. ” 2000 Elsevier Science Ltd. All rights reserved.

Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigated.

Simulation and experimental characterization of reservoir and via layout effects on electromigration lifetime

As schrinking of feature size in integrated circuits and increasing of packing density continue, it becomes incrementally important to take into account the interconnect layout features which can limit the risk of electromigration failure and improve the reliability of intervonnect systems. However, hardly any information is available on the reservoir and via layout effects on electromigration. In this paper, we characterized the influence of via count and current crowding effects on electromigration lifetime in different via and reservoir layouts design through simulation and experiments. We observe a negligible difference in electromigration lifteime for structures having the same reservoir area, irrespective of the contact/via configuration. The effect of current crowding on electromigration lifetime after an increasing of the current density stress was still small. The highest tensile stress point obtained from simulations coincides with the experimentally found void locations.

AN EMPIRICAL MODEL FOR EARLY RESISTANCE CHANGES DUE TO ELECTROMIGRATION

A new heuristic description for electromigration-induced early resistance changes is given. The basis is formed by two coupled partial differential equations, one for vacancies, and one for imperfections. These equations are solved numerically for a grain boundary bamboo structure. It is shown that this model is capable of simulating the typical effects as observed in early resistance change measurements. These early resistance changes are due to the redistributions of the vacancies and the generation of imperfections. Simulations are performed that closely match the measured resistance change curves.

Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism.

Mechanical stress evolution and the blech length: 2D simulation of early electromigration effects

Modeling of stress and electromigration at the microscopic level, in confined interconnect metallic lines with tungsten studs, can very well account for the resistance behaviour in time. The resistance change at saturation for a metallic line with blocking boundaries at both ends can be related, according to the model, to threshold product (jL)c found by Blech [1].

Progressive degradation in a-Si: H/SiN thin film transistors

In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive degradation model (PDM). According to PDM the degradation of the electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites and existing bulk defects in a-SiN:H transitional region.

Early resistance change and stress/electromigration modeling in aluminum interconnects

A complete description for early resistance change and two dimensional simulation of mechanical stress evolution in confined Al interconnects, related to the electromigration, is given in this paper. The model, combines the stress/ vacancy concentration evolution with the early resistance change of the Al line, that could be [1] a fast technique for prediction of the MTF of a line compared to the conventional (accelerated) tests.

Comprehensive physical modeling of NMOSFET hot-carrier-induced degradation

The role of hot-carrier-induced interface states in NMOSFETs is discussed. A new model is proposed based on measurements in several 0.7/spl mu/m CMOS technologies of different suppliers. Our model for the first time enables accurate interface state prediction over many orders of magnitude in time for all stress conditions under pinch-off and incorporates saturation. It can easily be implemented in a reliability circuit simulator, enabling more accurate NMOSFET parameter degradation calculations (e.g. /spl Delta/I/sub D/, /spl Delta/g/sub m/ etc.).