F. Ji

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH3-annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO2 interface.

Improved charge-trapping properties of TiON/HfON dual charge storage layer by tapered band structure

A TiON/HfON dual charge storage layer (CSL) with tapered bandgap structure is proposed for metal-oxide–nitride-oxide–silicon-type memory by using the inter-diffusion of Ti and Hf atoms near the TiON/HfON interface to form an intermixing layer of HfxTiyON with varying Hf/Ti ratio in the dual CSL during post-deposition annealing, as confirmed by transmission electron microscopy. The memory capacitor with TiON/HfON as dual-CSL shows a large memory window of 5.0 V at ±12 V for 100 μs, improved cycling endurance with little degradation after 105 cycles and good data retention with an extrapolated 10-yr window of 4.6 V at room temperature. These are highly associated with the tapered bandgap structure and appropriate trap distribution in the dual CSL. Therefore, the TiON/HfON dual-CSL structure provides a very promising solution for future charge-trapping memory applications.

Electrical properties of HfTiON gate-dielectric metal-oxide-semiconductor capacitors with different Si-surface nitridations

Electrical properties of HfTiON gate-dielectric metal-oxide-semiconductor (MOS) capacitors with different Si-surface nitridations in N2O, NO, and NH3 prior to high-k film deposition are investigated and compared. It is found that the NO-nitrided sample exhibits low interface-state density and gate leakage current, and high reliability. This is attributed to formation of a SiON interlayer with suitable proportions of N and O. The MOS capacitor with Hf0.4Ti0.6OxNy∕SiON gate dielectric stack (capacitance equivalent thickness of 1.52nm and k value of 18.9) prepared by NO surface nitridation has an interface-state density of 1.22×1011cm−2eV−1 and gate leakage current density of 6×10−4Acm−2 (Vg=1V). Moreover, only a small degradation of electrical properties after a stressing at 10MV∕cm for 3000s is observed for the NO-nitrided sample.

Improved Interfacial and Electrical Properties of Ge-Based Metal-Oxide-Semiconductor Capacitor With LaTaON Passivation Layer

The interfacial and electrical properties of Ge-based metal-oxide-semiconductor (MOS) capacitor with high-k gate dielectric of HfTiO and passivation interlayer of LaTaON are investigated. Experimental results show the Ge MOS with HfTiO/LaTaON gate-stacked dielectric exhibits low interface-state density (7.8 × 10¹¹ cm^-2 eV^-1), small gate-leakage current (7.88 × 10^-4 A cm^-2 at V_g - V_fb = 1 V), small capacitance equivalent thickness (1.1 nm), and large equivalent dielectric constant (27.7). X-ray photoelectron spectroscopy and transmission electron microscopy reveal that the improvements should be due to the fact that La/Ta-based oxide/oxynitride has excellent interface properties with Ge, and the LaTaON interlayer can effectively block the in-diffusion of oxygen and the out-diffusion of germanium, thus suppressing the growth of low-k GeO_x and intermixing between Ge and Hf.

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm−2 eV), small gate leakage current (8.6×10−4 A cm−2 at Vg−Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

A Novel MONOS Memory With High-

MIS capacitors with a high-κ HfLaON or HfLaO gate dielectric are fabricated by using a reactive sputtering method to investigate the applicability of the films as a novel charge-storage layer in a metal-oxide-nitride-oxide-silicon nonvolatile memory device. Experimental results indicate that the MIS capacitor with a HfLaON gate dielectric exhibits a large memory window, high program/erase speed, excellent endurance property, and reasonable retention. The involved mechanisms for these promising characteristics with HfLaON are thought to be in part from nitrogen incorporation leading to higher density of traps with deeper levels and, thus, higher trapping efficiency, stronger Hf-N and La-N bonds, and more stable atomic structure and HfLaON-SiO2 interface, as compared to the HfLaO dielectric.

\kappa

A model on subthreshold slope of UTB SOI MOSFETs is established and its validity is confirmed by comparing with the simulated results from technology computer aided design. Using the model, the impacts of k values of the gate dielectric and buried insulator on the subthreshold slope of the device are discussed. The results show that the subthreshold behaviors will be degraded when high-k gate dielectric is used due to enhanced fringing field effect, and however, can be improved by using low-k buried insulator.

HfLaON as Charge-Storage Layer

Storage properties of high-κ HfLaON or HfON dielectric as charge-storage layer in MONOS non-volatile memory device are comparatively investigated by fabricating MIS capacitors using reactive sputtering method. Larger memory window, higher program/erase speed, and reasonable retention were observed for the HfLaON MIS capacitor than the HfON MIS capacitor. This is probably because La incorporation in HfON could induce more traps with deeper levels and thus higher trapping efficiency, and more stable atomic structure compared to the HfON dielectric.

Influences of k values of gate dielectric and buried insulator on subthreshold slope of UTB SOI MOSFETs

In this paper, Si-MOS capacitors with HfTiO/SiON stack gate dielectric were fabricated by using Si-surface thermal passivation in NO and N2O ambients respectively and reactive co-sputtering technology. Results show that the sample pretreated in NO ambient has excellent interface properties, low gate leakage current density and high reliability. This is attributed to the formation of a SiON interlayer with suitable proportion of N and O, and N-barrier role of isolating Ti in HfTiO from Si of the substrate, thus effectively preventing the inter-diffusions of Ti and Si during post-deposition annealing.

Comparative study of high-k HfLaON and HfON as charge-storage layer of MONOS memory

HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds ∼1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700 °C for 30 s) can produce smooth surface, thus resulting in low gate leakage current.