F. K. A. Hamid

Simulation study of 25 nm PMOS FinFET fabrication with silicon co-implant

Silicon co-implantation into PMOS FinFET fabrication is presented. The co-implantation method is applied at the source and drain to enhance transportation properties of the devices. The device is fabricated using an industry oriented tool, Sentaurus TCAD. Performance assessment is performed on two electrical parameters, which are threshold voltage and driving current. The simulation results show that these parameters are strongly dependent on the co-implantation level. Threshold voltage is reduced with energy implantation of Silicon doped but increased with silicon implant dose concentration. The silicon co-implantation also positively affects the on-current as the on-state current significantly increased.

Impact of strain on electrical performance of Silicon Nanowire MOSFET

A 3-Dimensional (3D) strained Silicon Nanowire MOSFET simulation and inversion charge model are presented. The simulation studies are conducted based on electrical parameters of nanowires such as current and threshold voltage using a ATLAS TCAD simulator. The inversion charge model with Germanium fraction is formulated using a unified charge model. These characterization studies are performed to investigate the performance of Silicon Nanowire based on the strain effect. The simulation and modeling works have been compared with numerical simulations. Findings have shown that the strained Silicon Nanowire performs better compared to the unstrained Silicon Nanowire MOSFET, where the on-state current increased, threshold voltage shifted by 0.2 V and inversion charge density improved by 30%.

Explicit continuous charge-based compact model for long channel heavily doped surrounding-gate MOSFETs incorporating interface traps and quantum effects

An explicit solution for long-channel surrounding-gate (SRG) MOSFETs is presented from intrinsic to heavily doped body including the effects of interface traps and fixed oxide charges. The solution is based on the core SRGMOSFETs model of the Unified Charge Control Model (UCCM) for heavily doped conditions. The UCCM model of highly doped SRGMOSFETs is derived to obtain the exact equivalent expression as in the undoped case. Taking advantage of the undoped explicit charge-based expression, the asymptotic limits for below threshold and above threshold have been redefined to include the effect of trap states for heavily doped cases. After solving the asymptotic limits, an explicit mobile charge expression is obtained which includes the trap state effects. The explicit mobile charge model shows very good agreement with respect to numerical simulation over practical terminal voltages, doping concentration, geometry effects, and trap state effects due to the fixed oxide charges and interface traps. Then, the drain current is obtained using the Pao–Sahs dual integral, which is expressed as a function of inversion charge densities at the source/drain ends. The drain current agreed well with the implicit solution and numerical simulation for all regions of operation without employing any empirical parameters. A comparison with previous explicit models has been conducted to verify the competency of the proposed model with the doping concentration of , as the proposed model has better advantages in terms of its simplicity and accuracy at a higher doping concentration.

Simulation of Trigate FET with Semi-Cylindrical Channel to Reduce Corner Effect

Trigate Field Effect Transistor (FET) is one of the promising devices to overcome MOSFET scaling. However, major problems arised due to edge of the corner which introduced a high leakage current as well as reliability issues. In this work, we have introduced a method to reduce these issues by incorporating a semi-cylindrical channel through simulation. Based on simulated results, it was found that this method can minimize the leakage current. In addition, this structure makes the device less sensitive to temperature effect and more robust. Besides, radius variation can be used to reduce leakage current even smaller. It was found that the maximum drive current of this device is higher compared to reported silicon nanowire trigate MOSFET.