Fa Foster Dai

A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13

A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time resolution, small die size and low power consumption simultaneously. A pre-logic unit is developed to measure both positive and negative phase errors for DPLL applications. The TDC achieves a large detectable range of 12 bits with core area of 0.75 × 0.35 mm2 in a 0.13 μm CMOS technology. The total power consumption for the entire TDC chip is only 7.5 mW with a 1.5 V power supply, while operating at a clock frequency of 15 MSPS.

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This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mum 2P4M CMOS technology. The whole chip occupies a die area of 490 times 780 mum2 and consumes only 2.1 muW in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a -14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

CMOS Technology

This paper presents a novel direct digital frequency synthesis (DDFS) ROM compression technique based on two properties of a sine function: (a) piecewise linear technique to approximate a sinusoid, and (b) variation in the slope of the sinusoid at different phase angles. In the proposed DDFS architecture the ROM stores a few of the sinusoidal values, and the interpolation points between the successive stored values are calculated using linear arid nonlinear addressing schemes. The nonlinear addressing scheme is used to adaptively vary the number of interpolation points as the slope of the sinusoid changes, leading to a greatly reduced ROM size. The proposed architecture achieves a high compression ratio with a spurious response comparable to that of recent ROM compression techniques. To validate the proposed DDS architecture, the linear, nonlinear, and conventional DDS ROM architectures were implemented in a Xilinx Spartan II FPGA and their spurious performances were compared.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF–DC Rectifier

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.

A novel DDS using nonlinear ROM addressing with improved compression ratio and quantization noise

This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies 3.0 × 2.5 mm2 and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 μm SiGe BiCMOS technology with fT/fMAX = 200/250 GHz and tested in a CLCC-68 package.

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

A field-programmable-gate-array (FPGA)-based built-in self-test (BIST) approach that is used for adaptive control in mixed-signal systems is presented. It provides the capability to perform accurate analog functional measurements of critical parameters such as the third-order intercept point, frequency amplitude and phase responses, and noise figure. The results of these measurements can then be used to adaptively control the analog circuitry for calibration and compensation. The BIST circuitry consists of a direct digital synthesizer-based test pattern generator and a multiplier/accumulator-based output response analyzer. The BIST approach has been implemented in an FPGA-based mixed-signal system and used for actual analog functional measurements. The BIST measurements agree quite well with the results obtained with the traditional analog test equipment. The proposed BIST circuitry provides a unique means for high-performance adaptive control in mixed-signal systems.

24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13

This paper addresses the performance degradation of multiple-input multiple-output (MIMO) communication systems due to MIMO wireless transceiver radio frequency integrated circuits (RFIC) imperfections. The effects of signal coupling in RF front-end, frequency synthesizer phase noise, and the gain imbalance between different radio paths are investigated. These issues are explored by analytical derivations and results are verified by Monte Carlo simulations. The analytical model achieves a good agreement with the simulation results. The conclusion can serve as a useful reference for MIMO RFIC designers.

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This letter presents a novel quadrature voltage controlled oscillator (QVCO) implemented in a 47-GHz SiGe BiCMOS technology. The QVCO is a serially coupled LC VCO that utilizes SiGe heterojunction bipolar transistors for oscillation and metal oxide semiconductor field effect transistors for coupling. The SiGe BiCMOS QVCO prototype achieves about 14.6% tuning range from 4.3 to 5GHz. The phase noise of the QVCO is measured as -114.3 dBc/Hz at 2-MHz offset. The 5-GHz QVCO core consumes 6-mA current from a 3.3-V power supply and occupies 0.88mm2 area

m SiGe BiCMOS Technology

This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-mum SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed with more than 13 500 transistors, the quadrature DDS occupies an active area of 2.3 times 2.5 mm2 and a total die area of 3.0 times 3.0 mm2. The measured spurious-free dynamic range is approximately 26 dBc at a clock frequency 6.2 GHz. At the maximum clock frequency, the power consumption of the DDS is 2.5 W with 3.3- and 4.0-V power supplies for the digital and analog parts, respectively. The DDS thus achieves a power efficiency figure-of-merit of 5.04 GHz/W/phase. The DDS chips were packaged with 48-pin ceramic leadless chip carriers and air cooling was used during the measurement.

FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems

This paper presents an 8-18 GHz wideband receiver with recursive super-heterodyne topology. A multi-feedback technology is utilized in the LNA design for the input matching over the wide frequency range in X- and Ku-band. In order to save power, both the RF and IF signals share a tunable transconductance stage. The IF output of the first mixer is fed back into the tunable input stage for IF amplification in a recursive manner, which significantly enhances the gain tuning without increasing the power. The wideband receiver MMIC is implemented in a 0.13 SiGe BiCMOS technology and achieves a 6.7-7.8 dB noise figure. The receiver average gain over the frequency range is measured as 53 dB maximum gain with 20 dB continual tuning and 36 dB discrete tuning. The average output P1dB over the frequency range is measured as 10 dBm at maximum gain. The receiver dissipates only 180 mW with a 2.2 V power supply.