Richard C. Jaeger

Heat sink optimization with application to microchannels

The equations governing the fluid dynamics and combined conduction/convection heat transfer in a heat sink are presented in dimensionless form for both laminar and turbulent flow. A scheme presented for solving these equations permits the determination of heat sink dimensions that display the lowest thermal resistance between the hottest portion of the heat sink and the incoming fluid. Results from the present method are applied to heat sinks reported by previous investigators to study effects of their restrictions regarding the nature of the flow (laminar or turbulent), the ratio of fin thickness to channel width, or the aspect ratio of the fluid channel. Results indicate that when the pressure drop through the channels is small, laminar solutions yield lower thermal resistance than turbulent solutions. Conversely, when the pressure drop is large, the optimal thermal resistance is found in the turbulent region. With the relaxation of these constraints, configurations and dimensions found using the present procedure produce significant improvement in thermal resistance over those presented by all three previous studies. >

Silicon piezoresistive stress sensors and their application in electronic packaging

Structural reliability of integrated circuit (IC) chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, operating temperatures, and the use of a wide range of low-cost packaging materials. A powerful method for experimental eval- uation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezore- sistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented. In the absence of die failure, packaging-induced stresses result in changes in the parametric performance of circuitry on the die, and the theory discussed here can be used to predict such changes. Index Terms—Electronic packaging, piezoresistive, stress sensor, test chip.

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling. >

A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13

A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time resolution, small die size and low power consumption simultaneously. A pre-logic unit is developed to measure both positive and negative phase errors for DPLL applications. The TDC achieves a large detectable range of 12 bits with core area of 0.75 × 0.35 mm2 in a 0.13 μm CMOS technology. The total power consumption for the entire TDC chip is only 7.5 mW with a 1.5 V power supply, while operating at a clock frequency of 15 MSPS.

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This paper demonstrates that the intrinsic piezoresistive response of the MOSFET channel is independent of length. The reported fall-off of the piezoresistive response of the transistor in short channel devices is shown to be the result of parasitic series resistance in the source of the transistor. At the same time, the experimental results demonstrate that the threshold voltage of the devices is essentially independent of stress. The results are verified for three independent processes.

CMOS Technology

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power. >

Piezoresistive characteristics of short-channel MOSFETs on (100) silicon

The variation of the piezoresistive coefficients from several rosettes on the same die, the same wafer, and finally at different doping levels across a number of wafers was examined. A thorough error analysis of the method of applying a known uniaxial state of stress using a four-point bending (4PB) fixture was completed. A sensor error analysis demonstrated that it is very difficult to determine accurate values for the sum ( pi /sub 11/+ pi /sub 12/) using the common two-element rosette, particularly in p-type material. However, an empirical equation was found that provides an estimate for this coefficient. The second piezoresistive coefficient pi /sub 44/ can be measured accurately. However, the results presented for pi /sub 44/ differ from those of previous authors by some 33%. Thus, it appears necessary to measure this value for a given wafer lot. >

A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier

Abstract During the study of depletion mode MOSFET behavior at low temperatures, unusual changes in the threshold characteristics of the devices were observed. First, the effectiveness of the donor implantation in producing a negative threshold voltage shift was significantly reduced. At the same time the substrate sensitivity was found to be substantially reduced. A third observation was the existence of an unusual structure in the subthreshold region of the device at low temperatures. Computer simulation is used to explore these observations and to demonstrate that they are caused by impurity freezeout as temperature is reduced. The computer simulation program, usable over the temperature range 50–350 K, is discussed, and a threshold definition suitable for numerical analysis of devices with arbitrary channel structures is developed.

Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixture

Successful application of piezoresistive sensors for stress measurement requires both properly designed sensors and accurately calibrated values of the piezoresistive coefficients as well as a knowledge of potential sources of error that may be encountered during sensor application. In this work, results of analyses of errors associated with the design, calibration and application of piezoresistive stress sensors fabricated on (100) silicon are presented. In particular, sensor rotational alignment errors during fabrication and resistance measurements errors during calibration have strong effects on the values of the piezoresistive coefficients that are extracted from the calibration process. Also, calibration errors induced by mismatches in the resistor values and/or the actual piezoresistive coefficients of the various resistors in a sensor rosette have been quantified, and the importance of using data acquired only from well-matched resistor rosettes is demonstrated. Finally, it is shown that temperature measurement errors play a pivotal role in determining accuracy of the results obtained during calibration and application of these sensors. >

Temperature dependent threshold behavior of depletion mode MOSFETs: Characterization and simulation

An interesting approach to improving the performance of MOS off-chip drivers has previously been described (see ibid., vol.10, no.2, p.106 (Apr. 1975)). The selection of the optimization criterion is discussed.