Fabian Vargas

SEU-tolerant SRAM design based on current monitoring

We present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error correction.<<ETX>>

A new hybrid fault detection technique for systems-on-a-chip

Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.

Electrocardiogram pattern recognition by means of MLP network and PCA: a case study on equal amount of input signal types

This work proposes a system to help the doctor to detect cardiac arrhythmia. As reference, it uses the normal, fusion and PVC signals of the MIT database. Then, we extract the principal characteristics of the signal by means of the principal component analysis (PCA) technique. One key point in this work is the input signals extraction, which are captured in the same amount. So, the number of segments for each signal is the same. After signal preprocessing, they are applied to a multilayer perceptron (MLP). The MLP with 5 neurons was verified to have the best accuracy. Based on this idea (the use of the same information amount for all input signal types), we achieved better results in comparison with other works in the field. This consideration is very important due to the fact that the ANN could be more sensible to the signal type with major predominance.

Hybrid Soft Error Detection by Means of Infrastructure IP Cores

High integration levels, coupled with the increased sensitivity to soft errors even at ground level, make the task of guaranteeing adequate dependability levels more difficult then ever. In this paper, we propose to adopt low-cost infrastructure-intellectual-property (I-IP) cores in conjunction with software-based techniques to perform soft error detection. Experimental results are reported that show the effectiveness of the proposed approach.

A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results

This paper presents the architecture of a CMOS static RAM which is tolerant to radiation-induced upsets. It employs transient current sensing circuits to achieve concurrent, event-driven SEU detection and correction. Tests with simulated upsets and preliminary radiation tests showed the detection of all upsets and proved the effectiveness of the approach.

On the proposition of an EMI-based fault injection approach

The following paper describes a new approach to perform physical fault injection in electronic systems. The approach is settled around a gigahertz transverse electromagnetic (GTEM) cell, which is employed in a controlled process to inject faults in the system under test (SUT). The assumed fault models are delay faults (provoked by signal propagation delay increase in SUT critical paths, thus resulting in de-synchronization between the computed data to be latched and the clock signal) and bit-flips (i.e., corruption of static data stored in memory elements).

Design of built-in current sensors for concurrent checking in radiation environments

A technique for concurrently checking faults in static CMOS circuits is proposed. It performs concurrent monitoring of static current by means of built-in current sensors (BICS) and detects the leakage current that accompanies the parametric shifts. Using BICs also allows the selection of high-quality circuits during manufacturing testing, resulting in a higher mean time to failure. >

Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

High integration levels, coupled with the increased sensitivity to soft errors even at ground level, make the task of guaranteeing adequate dependability levels more difficult then ever. In this paper, we propose to adopt low-cost infrastructure-intellectual-property (I-IP) cores in conjunction with software-based techniques to perform soft error detection. Experimental results are reported that show the effectiveness of the proposed approach.

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction

This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding and decoding algorithms, and zero fault-detection latency time for multiple error detection when compared to conventional techniques. The approach is based on the use of Built-In-Current-Sensors (BICS) to detect the abnormal current dissipation in the memory power-bus to improve the reliability of H-Tree SRAM memories. This abnormal current is the result of a single-event upset (SEU) in the memory, and it is generated during the inversion of the state of the memory cell being upset (bit-flip). We demonstrate the assertions of the proposed approach with HSPICE simulations, and a reliability analysis that combines BICS with single-parity bit (or Hamming codes) per SRAM word to perform error correction. Furthermore, the basic infrastructure provided by this approach can also be used to dynamically reconfigure the SRAM memory to save power, and to leverage fabrication yield.