Letícia Maria Bolzani Poehls

Hierarchical identification of NBTI-critical gates in nanoscale logic

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical gates in nanoscale logic. The method is based on static timing analysis that provides delay critical paths under NBTI-induced delay degradation. An analysis on these critical paths is performed in order to select the set of gates that have the highest influence on circuit aging. These gates are to be hardened against NBTI aging effects guaranteeing correct circuit behavior under the given timing and circuit lifetime constraints. The proposed approach is demonstrated on an industrial ALU circuit design.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

This work proposes a novel methodology to evaluate SRAM-based FPGAs susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, TotalIonizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGAs VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGAs BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined Effects of Conducted EMI and TID

This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

Identifying NBTI-Critical Paths in Nanoscale Logic

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It may increase the switching threshold voltage of pMOS transistors and as a result slow down signal propagation along the paths between flip-flops thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical paths in nanoscale logic that is based on analyzing combination in different degrees of the three parameters: delay-critical paths, gate input signal probability and the gate fan-out degree along the paths. Further the identified NBTI-critical path can be used e.g. for introduction of aging sensors circuitry, rejuvenation stimuli generation, etc. The proposed approach is demonstrated on an industrial ALU circuit design.

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging

This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.

Evaluating the Effects of Combined Total Ionizing Dose Radiation and Electromagnetic Interference

Although measurement methods for Electromagnetic (EM) immunity and Total Ionizing Dose (TID) radiation are highly standardized, little effort has been made though, to evaluate the behavior of embedded systems under the combined effects. Considering realistic environment conditions only the measurement of these effects can guarantee reliable embedded systems for critical applications. A configurable platform to evaluate the effects of TID radiation and EM Interference (EMI) on embedded systems is presented. Experiments illustrate the consequences regarding delay and fault occurrence probability as well as current consumption and minimum power supply.

Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study

Microprocessor-based systems robustness under Single Event Effects is a very current concern. A widely adopted solution to make robust a microprocessor-based system consists in modifying the software application by adding redundancy and fault detection capabilities. The efficiency of the selected software-based solution must be assessed. This evaluation process allows the designers to choose the more suitable robustness technique and check if the hardened system achieves the expected dependability levels. Several approaches with this purpose can be found in the literature, but their efficiency is limited in terms of the number of faults that can be injected, as well as the level of accuracy of the fault injection process. In this paper, we propose FPGA-based fault injection techniques to evaluate software robustness methods under Single Event Upset (SEU) as well as Single Event Transient (SET). Experimental results illustrate the benefits of using the proposed fault injection method, which is able to evaluate a high amount of faults of both types of events.

Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices

Graphene, one of the viable candidates to replace Silicon in the next generation electronic devices, is pushing the research community to find new technological solutions that can exploit its special characteristics. Among the proposed approaches, the electrostatic doping represents a key option. It allows the implementation of equivalent pn-junctions through which is possible to build a new class of reconfigurable logic gates, the devices analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22nm. This work explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, has been analyzed and mapped at a higher level of abstraction using proper fault models. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.

Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity

The roadmap for standardization of electromagnetic (EM) immunity measurement methods has reached a high degree of success with the IEC 62.132 proposal. The same understanding can be taken from the MIL-STD-883H for total ionizing dose (TID) radiation. However, no effort has been performed to measure the behavior of electronics operating under the combined effects of both, EM noise and TID radiation. For secure embedded systems and systems-on-chip (SoC) devoted to critical applications, these combined-effect measurements are mandatory. In this paper, we present a configurable platform devoted for combined tests of EM immunity and TID radiation measurements of prototype embedded systems. The platform attends the IEC 62.132–2 (for radiated EM noise), IEC 61.0004–17 and IEC 61.0004–29 (for conducted EM disturbance) and 1019.8 method for TID Test Procedure of MIL-STD-883H.