Fabrizio Vacca

Implementation of a Flexible LDPC Decoder

Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.

Interconnection framework for high-throughput, flexible LDPC decoders

This paper presents a possible interconnection structure suitable for being used in a flexible LDPC decoder. The main feature of the proposed approach is the possibility of implementing parallel or semi-parallel decoders with a reduced communication complexity. To the best of our knowledge this is the first work detailing the implementation of a fully flexible LDPC decoder, able to support any type of code. To prove the effectiveness of this approach, a complete decoder has been implemented on a XC2V8000, achieving a decoding throughput of 529 Mbps on a (1920, 640) code

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm

This paper explores the possibility of building a flexible Low Density Parity Check (LDPC) decoder using a Network On Chip communication infrastructure. Even if this idea is not completely new, previously published works suffered from an excessive area occupation and their practical impact has been very limited. In the following we analyze two possible NOCs specifically designed for the LDPC case. From synthesis results it can be observed how the proposed networks outperform previous implementations in terms of active area with no significant bandwidth loss. Finally to prove the effectiveness of the proposed approach a complete, partially parallel LDPC decoder design is resented and characterized in terms of throughput and area occupation.

Embedded IWT evaluation in reconfigurable wireless sensor network

This paper presents the evaluation of a low complexity discrete wavelet transform for image compression in a critical scenario such as the wireless sensor network one. Due to the increasing interest towards the possibility of developing wireless networks of small sensors with embedded processing capabilities, IC designers have to face new challenges. In particular not only power consumption issues but also algorithm complexity can tackle sensors feasibility. Moreover, a remarkable degree of reconfigurability has to be granted to reach high flexibility. The analysis proposed in this paper is based on the development of a parametric IP mapped on different physical layers. The reported measures show that very interesting low-energy figures can be achieved on modern CPLD devices.

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring

The on-line monitoring and detection of defects in laser welding is a basic manufacturing requirement in several applicative contexts, as vehicle assembly in automotive production. This work presents the FPGA implementation of time-frequency analysis algorithms as an effective solution compared with pure software implementation based on different modern processors. In particular the proposed FPGA based approach not only satisfies the processing constraints of the considered application, but still offers a high degree of flexibility and modularity.

DSP implmentation of a low complexity motion detection algorithm

The use of video cameras for video surveil- lance and monitoring has always been very important, but nowadays, due to the need to fight terrorism and crime, a real explosion in the use of technological devices such as web cams and hidden cameras is taking place. In this work we investigate a low-complexity motion detection algorithm recently proposed in the literature. Starting from the algorithm itself, the aim of this paper is twofold: to improve the existing work making it robust against illumination changes, and to port the proposed solution on a DSP board.

Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming

An energy efficient architecture for the discrete cosine transform is presented. The proposed IP is intended to be used as the transform stage in a mobile H.263 codec. In particular, it seems well suited for an FPGA implementation since, after a complete place and route process, it is able to sustain a full-motion PAL video streaming operating at a frequency of 74 MHz with a dynamic power dissipation of just 39 mW.

FPGA system-on-chip soft IP design: a reconfigurable DSP

In this paper a novel architecture for a scalable DSP core is proposed. Due to the increase of system resources available on last generation FPGA, the System-on-Chip paradigm can be borrowed from classical silicon implementations into reconfigurable environments. Presently, off-the-shelf devices suffer the need for remarkable static power consumption: however it is forecastable that technology improvements will extend FPGA usage to mobile systems. Despite the increasing importance gathered by reconfigurable computing, a lack of retargetable soft-processor IP is felt. In particular, this IP aims to fill the existing gap between specific coprocessor units and general purpose soft cores. The proposed architecture exhibits interesting figures both in terms of area occupation as well as maximum operative clock frequency. In order to validate the system performance, some common telecommunication algorithms have been mapped on the DSP. Good experimental results have been obtained running at 89 MHz on a XILINX XCV1000.

System architecture for error-resilient, embedded JPEG2000 wireless delivery

With new, third generation mobile terminals several multimedia-based applications will be soon available. The reliable transmission of audiovisual content will probably become one of the most asked services. On the other hand, when wireless delivery is addressed, it would be desirable to reach very high compression ratio keeping a good image perceptual quality. With these requirements the choice of JPEG2000 as the source encoding stage assures excellent results. However a non-ideal wireless network could seriously affect the received image decoding, despite JPEG2000s error resilience capabilities. In this paper a flexible DSP/FPGA system with high error-resilience features is proposed. Experimental results show very promising visual quality, with a limited complexity overhead, even in the presence of a mean loss rate of 10%.

Parametric FPGA early-late DLL implementation for a UMTS receiver

Third generation communication schemes, mainly based on the W-CDMA access technique, are replacing second generation ones both in the US and in EU countries. CDMA makes possible simultaneous communications, spreading the users information over a large frequency range by means of orthogonal codes. One of the main problems of this type of communication is the need for exact alignment between the received sequence and the locally despreading code. The early-late block is devoted to maintaining this alignment using a delay locked loop, provided that the first alignment is performed by the synchronizer block. A reconfigurable early-late tracking loop architecture, for SDR (software defined radio) implementation, is proposed. Very promising results have been obtained from logical synthesis and from physical implementation on a Xilinx XCV100E (48.7 Mhz, 616 FFs, 719 LUTs).