Libero Dinoi

Design of variable-rate irregular LDPC codes with low error floor

In this paper we propose a semi-random technique to design irregular LDPC codes with low error floor. In particular, the suggested technique is related to a popular class of irregular LDPC codes that can be encoded in linear time, and tries to avoid both low-weight codewords and near-codewords, which limit the performance of the belief propagation decoder. Besides, an easy and effective rule to design puncturing patterns for this class of LDPC codes is provided. The effectiveness of the new design criteria is proved by comparison with literature results.

Variable-size interleaver design for parallel turbo decoder architectures

In this paper, we propose two techniques to design good S-random interleavers, to be used in parallel and serially concatenated codes with interleavers. The interleavers designed according to these algorithms can be shortened, in order to support different block lengths in such a way that all the permutations obtained by pruning, when employed in a parallel turbo decoder, are collision-free. The first technique, suitable for short and medium interleavers, guarantees the same performance of nonparallel interleavers in terms of spreading properties, simulated frame-error probabilities, and obtainable minimum distance of the actual codes. The second algorithm, to be used for large block lengths, permits achieving high degrees of parallelism at the price of a slight degradation of the spread properties, and also to change the degree of parallelism on-the-fly. The operations of a parallel turbo decoder employing these interleavers are described, and an example of the advantages of the proposed techniques is provided in a realistic system framework.

Design of fast-prunable S-random interleavers

In this paper, a technique to obtain good prunable S-random interleavers to be used in parallel and serially concatenated codes with interleavers is proposed: The new design is based on an algorithm to extend the interleaver size in a wide interval of values, while keeping good spreading properties in the whole range. Then, a modified pruning technique to be used for this class of interleavers is proposed: It is shown that it produces good interleavers also when applied to nonprunable S-random permutations. Results are given in terms of spreading parameters, obtainable free distance of the actual codes, and simulated frame-error probabilities. They show that the designed interleavers behave in the whole size range as optimally designed interleavers for each size. Different pruning algorithms are described and their complexity, crucial for their feasibility, is analyzed. Finally, the tradeoffs between area savings and complexity are discussed in a realistic example.

Design of versatile eIRA codes for parallel decoders

In this paper we propose a semi-random technique for the generation of a class of eIRA codes (a popular class of irregular LDPC codes that can be encoded in linear time) suited to partially parallel decoder implementations. The suggested technique tries to avoid both low-weight codewords and nearcodewords, which limit the performance of the belief propagation decoder. Its effectiveness is verified by comparison with literature results. The obtained codes are versatile, in terms of code-rate and block length, and they are characterized by a low error floor.

eIRA Codes for Coded Modulation Systems

In this paper we discuss the design of linear time encodable extended irregular repeat-accumulate (eIRA) codes for bit-interleaved coded modulation (BICM) systems. We interpret eIRA codes as a particular instance of the recently introduced multi-edge type (MET) low-density parity-check (LDPC) codes. This allows us to take into account during the design step both the systematic nature of these codes and the different level of protection given to each bit by the choice of input alphabet and mapping function. Furthermore, we extend to the eIRA-BICM case the method used by Roumy et al., IEEE Trans. Inf. Theory, 2004, to optimize LDPC codes for the binary input AWGN (bi-AWGN) channel. This method is based on EXIT functions and leads to a linear program. Using this method we design capacity-approaching eIRA codes for 4PAM and 8PSK. For both short and long block lengths these codes have performance approximately 0.1 dB worse than LDPC codes optimized with density evolution and with similar decoding complexity.

Design of Prunable Interleavers for Parallel Turbo Decoder Architectures

In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided

Design of a VLSI Decoder for Partially Structured LDPC Codes

The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edges of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

Design issues in the implementation of versatile, high-speed iterative decoders

The ever increasing demand for high data rate communication, and the use of radio resource management techniques requiring frame-by-frame adaptive coding/modulation to match user demands and channel conditions, pose a number of crucial problems to the design of versatile, high-speed iterative decoders, for both turbo-like and low-density parity-check codes. Among them, we mention: The modification of the Soft-Input Soft-Output (SISO) algorithm in a way that permits its implementation using several parallel processors working independently on segments of the received frame. The collisions in the process of reading/writing into/from the memory by the parallel processors. The design of prunable interleavers covering a wide range of information and/or code words lengths while keeping good spreading properties. The design of codes yielding a wide range of code rates with good performance for the range of probability of error of interest. The paper will touch all the previous points, offering state-of-the art solutions and examples showing their performance. Copyright

A permutation decomposition based algorithm for the design of prunable interleavers for parallel turbo decoder architectures

In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided.