Fadi R. Shahroury

The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications

The CMOS integrated 3-GHz to 11-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-mum CMOS technology. The designed UWB transmitter is integrated with a 2:1 frequency divider, a quadrature up-conversion mixer, a balanced RF amplifier, and a 3-stage cascaded poly-phase filter. The technique of inductance peaking has been adopted to achieve 14 -band operation for UWB applications. The transmitter has an average conversion gain of 12.8 dB with the gain ripple of around plusmn1.4 dB among the whole frequency band. The average input 1-dB compression point (IP-1dB) of the 14 bands is -12.2 dBm and the average output 1-dB compression point (OP-1dB) of the 14 bands is -0.4 dBm. The transmitter dissipates the power of 53.1 mW from the supply voltage of 1.2 V and occupies the chip area of 1930times1635 mum2. This chip is designed in 0.13-mum 1P8M CMOS technology and under fabrication.

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.

A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network

In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mum 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF min of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 mA from the supply voltage of 1 V.

A new modulation scheme for low power consumption and small size passive RFID tags

This paper presents the simulation of a new modulation scheme for passive RFID systems. The proposed modulation scheme can be used to achieve minimum RFID tag chip size with low power consumption simultaneously. The modulation scheme is tested by a carrier of 900MHz and data rate of 20Kbps. The simulation results have shown that the proposed modulation scheme reserves the continuity of the carrier signal, such as FSK & PSK. Meanwhile, the proposed modulation scheme can be detected by a low power consumption demodulator, such as OOK & ASK.

Low power passive RFID transponder frontend design for implantable biosensor applications

This paper presents a passive 13.56 MHz RFID transponder frontend design using 0.18 µm CMOS Technology for implantable biosensor applications. Power is provided to the system through a dual output full wave rectifier that provides power at two different voltage levels; the low level to the transponder frontend to reduce its power consumption and the high level to the biosensor to increase its dynamic range. The low voltage operation of the frontend is supplemented further by a current starved design reducing its power consumption to a minimal and leaving most available power to the biosensor. The design is verified using HSPICE Simulation showing a maximum frontend power consumption of only 6.5 µW and leaving at least 88% of the available power for the biosensors operation.

A Low -- Power and High -- Efficiency CMOS Transmitter for Wireless Sensor Network Application

This paper presents the design and simulation of the front-end low power transmitter for wireless sensor network application. The transmitter features simple circuitry with circuit techniques that reduce the power consumption and gives higher efficiency. The used modulation scheme is a modified version of ASK with better continuity to make it eligible for Wireless Passive Sensor Networks applications. The proposed transmitter features simple circuitry (smaller size), It operates in the ISM band (902-928 MHz) at 50 Kbps data rate. It achieves -6 dBm output power consuming 1.13 mW from a 1.8 V power supply. It was implemented and simulated using 0.18 um CMOS technology.

The Design and Optimization of Low-Voltage Pseudo Differential Pair Operational Transconductance Amplifier in 130 nm CMOS Technology

This paper presents low-voltage pseudo differential pair operational transconductance amplifier (OTA) circuit designed and simulated in 130 nm CMOS technology. The imperialist competitive algorithm (ICA) is used to optimize the DC gain, common-mode rejection ratio (CMRR), and power dissipation of the presented OTA. The cost function of ICA is evaluated in the form of simulation-based rather than equation-based to increase the precision of the final results. The simulation results after optimization show that the proposed OTA has DC gain of 37.5 dB, CMRR of 37.5 dB, and maximum signal swing at the output of 210 mV, with power consumption of 200uW from power supply of 0.5V.