Mahmood Mohammed

All-Graphene Planar Double-Quantum-Dot Resonant Tunneling Diodes

This paper proposes a new class of resonant tunneling diodes (RTDs) that are planar and realizable with a single graphene nanoribbon. Unlike conventional RTDs, which incorporate vertical quantum well regions, the proposed devices incorporate two confined planar quantum dots within the single graphene nanoribbon, giving rise to a pronounced negative differential resistance (NDR) effect. The proposed devices, termed here as planar double-quantum-dot RTDs, and their transport properties are investigated using quantum simulations based on nonequilibrium Greens function formalism and the extended Huckel method. The proposed devices exhibit a unique current-voltage waveform consisting of a single pronounced current peak with an extremely high, in the order of 104, peak-to-valley ratio. The position of the current peak can be tuned between discrete voltage levels, allowing digitized tunability, which is exploited to realize multi-peak NDR devices.

Highly Effective Conductance Modulation in Planar Silicene Field Effect Devices Due to Buckling

Silicene is an exciting two-dimensional material that shares many of graphene’s electronic properties, but differs in its structural buckling. This buckling allows opening a bandgap in silicene through the application of a perpendicular electric field. Here we show that this buckling also enables highly effective modulation of silicene’s conductance by means of an in-plane electric field applied through silicene side gates, which can be realized concurrently within the same silicene monolayer. We illustrate this by using silicene to implement Self-Switching Diodes (SSDs), which are two-dimensional field effect nanorectifiers realized within a single silicene monolayer. Our quantum simulation results show that the atomically-thin silicene SSDs, with sub-10 nm dimensions, achieve a current rectification ratio that exceeds 200, without the need for doping, representing a 30 fold enhancement over graphene SSDs. We attribute this enhancement to a bandgap opening due to the in-plane electric field, as a consequence of silicene’s buckling. Our results suggest that silicene is a promising material for the realization of planar field effect devices.

Monolayer MoS2 self-switching diodes

This paper presents a new molybdenum disulphide (MoS2) nanodevice that acts as a two-terminal field-effect rectifier. The device is an atomically-thin two-dimensional self-switching diode (SSD) that can be realized within a single MoS2 monolayer with very minimal process steps. Quantum simulation results are presented confirming the devices operation as a diode and showing strong non-linear I-V characteristics. Interestingly, the device shows p-type behavior, in which conduction is dominated by holes as majority charge carriers and the flow of reverse current is enhanced, while the flow of forward current is suppressed, in contrast to monolayer graphene SSDs, which behave as n-type devices. The presence of a large bandgap in monolayer MoS2 results in strong control over the channel, showing complete channel pinch-off in forward conduction, which was confirmed with transmission pathways plots. The device exhibited large leakage tunnelling current through the insulating trenches, which may have been due to...

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

This paper presents a 10 Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS and is capable of operating with a 29.5mV internal eye opening and a 67mV external eye opening at the input pads. It consumes 69uW from a 0.9V supply at 10 Gbps and properly asserts an LOS state in 6.8 nsec. A novel comparator topology, which is a part of the LOS circuit, is also presented. It compares a differential input to a differential reference voltage. Design and layout were implemented using Synopsys Custom Designer with 28nm CMOS device models. The LOS detector can reduce power consumption and bit error rate (BER) of serial transceivers.

Methodology for designing and verifying switched-capacitor sample and hold circuits used in data converters

This study presents a full methodological approach to designing and verifying differential sample and hold switched-capacitor circuits generally used in analogue-to-digital converters (ADCs). It provides a step-by-step process for translating system requirements such as signal-to-noise ratio and sampling frequency into ADC requirements and subsequently into operational amplifier topology and specifications. It also includes the design process of a switched-capacitor common mode feedback circuit to control the common mode output voltage. Furthermore, this study discusses the noise aspects of the switched-capacitor circuits. It also provides practical methods for verifying the stability of the system by using step voltage and step current techniques. A design and simulation example for a differential sample and hold switched-capacitor circuit operating in a system requiring a 5 MHz sampling frequency and a 6-bit ADC is provided. Mentor Graphics CAD tools were used in the design and the simulations process by using 180 nm complementary metal oxide semiconductors (CMOS) device models. This study can be used as a resource for the design engineers in the industry as well as the universities teaching graduate level advanced electronics and data converter courses.

Design of a voltage reference circuit based on subthreshold and triode MOSFETs in 90nm CMOS

This work presents a new design of a precision voltage reference circuit using MOSFET transistor devices operating in the subthreshold region. Also, a triode region MOSFET has been deployed instead of using resistors. The circuit has been designed and simulated in 90 nm CMOS technology. A reference voltage of 281 mV is obtained with Line Sensitivity, LS, of 0.23% in a supply voltage range of (0.8 V-1.65 V). The Temperature Coefficient, TC, is 125 ppm/°C through a temperature range of (0-85) °C The Power Supply Rejection Ratio (PSRR) is -48 dB at 50 Hz and -26 dB at 1 MHz. Finally, the power consumption is 11.31 μW and the coefficient of process variations is 0.29%. The design has been simulated using Synopsys Custom Designer and HSPICE CAD tools.

Design of a sub 1-V MOSFET based voltage reference circuit operating in subthreshold region

This paper presents the design and implementation of a precision voltage reference circuit using MOSFETs operating in the subthreshold region. It also shows the effect of technology scaling in designing voltage reference circuits. The circuit has been design and simulated in 28nm and 90nm CMOS technologies. For the 28nm technology, the circuit provides a reference voltage of 225 mV with a line sensitivity of 0.5%. The minimum and the maximum supply voltages are 0.9V and 3.25V, respectively. An average temperature coefficient of 138.5 ppm/°C, through a temperature range of (-20-150) °C, is achieved. Moreover, the power supply rejection ratio is -62dB at 50Hz and -49dB at 100 KHz. For the 90nm technology, a reference voltage of 115mV is obtained with a line sensitivity of 3.1% and a supply voltage as low as 0.25V. The temperature coefficient is 518 ppm/ °C, through a temperature range of (-20-80) °C, whereas the power supply rejection ratio is -31dB at 50Hz and -49dB at 100 KHz. The design is verified using Synopsys Custom Designer and HSPICE CAD tools.

Low power passive RFID transponder frontend design for implantable biosensor applications

This paper presents a passive 13.56 MHz RFID transponder frontend design using 0.18 µm CMOS Technology for implantable biosensor applications. Power is provided to the system through a dual output full wave rectifier that provides power at two different voltage levels; the low level to the transponder frontend to reduce its power consumption and the high level to the biosensor to increase its dynamic range. The low voltage operation of the frontend is supplemented further by a current starved design reducing its power consumption to a minimal and leaving most available power to the biosensor. The design is verified using HSPICE Simulation showing a maximum frontend power consumption of only 6.5 µW and leaving at least 88% of the available power for the biosensors operation.

Negative differential resistance in planar graphene quantum dot resonant tunneling diodes

Negative differential resistance (NDR), an electronic property present in resonant tunneling diodes, enables high performance terahertz frequency oscillators and multi-state logic and memory devices. An important measure of NDR is the peak-to-valley current ratio (PVCR) and this has been extremely lacking in solid-state NDR devices. Here we show how a dimensional mismatch between the quantum dot and the electrodes of a planar graphene Double Barrier Resonant Tunneling Diode (DB-RTD) greatly enhances the PVCR of the device up to a ratio of 103. Our findings suggest a promising future for the application of planar graphene quantum dot devices in next generation electronics.

A 10Gbps differential low-power loss of signal detector for AC-coupled serial transceivers in 28nm CMOS technology

This work presents a differential low-power 10Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS technology. It includes a novel comparator circuit that compares a differential input signal to a differential reference voltage with minimal sensitivity to the common mode voltage of the input signal. The LOS detector is capable of properly detecting a valid signal that has an external eye opening as low as 85mV and an internal eye opening as low as 36mV at the input pads. It asserts LOS if the external eye opening is below 50mV. It consumes 113uW from a 0.9V nominal power supply at 10Gbps date rate and properly asserts an LOS state in 25.5nS at typical corner operation. It occupies 0.00169mm2 of area. In simulations that include metal parasitic resistance and capacitance, the detector is shown to withstand process, voltage and temperature (PVT) variations and satisfy the commercial operating temperature range. The design and layout of the system were implemented in Synopsys Custom Designer using 28nm CMOS device models.