Fahim Rahman

An Aging-Resistant RO-PUF for Reliable Key Generation

Physical unclonable functions (PUFs) have emerged as a promising security primitive for low-cost authentication and cryptographic key generation. However, PUF stability with respect to temporal variations still limits its utility and widespread acceptance. Previous techniques in the literature have focused on improving PUF robustness against voltage and temperature variations, but the issues associated with aging have been largely neglected. In this paper, we address aging in the popular ring oscillator (RO)-PUF. We propose a new aging-resistant design that reduces sensitivity to negative-bias temperature instability and hot-carrier injection stresses. Simulation results demonstrate that our aging-resistant RO-PUF (ARO-PUF) can produce unique, random, and more reliable keys. On an average, only 3.8% bits of an ARO-PUF flip over a ten-year operational period because of aging, compared with a 12.8% bit flip for a conventional RO-PUF. The proposed ARO-PUF allows us to eliminate the need for error correction by adding extra ROs. The result shows that an ARO-PUF saves ~32x area overhead compared with a conventional RO-PUF with required error correction schemes for a reliable key.

A pair selection algorithm for robust RO-PUF against environmental variations and aging

Physically Unclonable Functions (PUFs) have emerged as a promising security primitive for low-cost authentication and cryptographic key generation. However, PUF stability with respect to temporal variations still limits its utility and widespread acceptance. Previous techniques in the literature have focused on improving PUF robustness against voltage and temperature variations, but the issues associated with aging have been largely neglected. In this paper, we propose a reliable pair selection algorithm (RePa) that can generate reliable keys from an RO-PUF under aging, voltage, and temperature variations. The RePa approach selects RO pairs with both initial frequency difference and aging rate/slope in mind. The aging slope is predicted by exploiting correlation that exists between frequency variation with respect to voltage and frequency variation with respect to aging. We evaluate RePa with simulations to show that it achieves significant improvement over the current state of the art in terms of reliability and cost. The proposed approach can achieve ~ 3.0x more robust key with only ~ 2.3x more ROs required than the conventional RO-PUF pair selection for the same key size.

Introduction to Cyber-Physical System Security: A Cross-Layer Perspective

Cyber-physical systems (CPS) comprise the backbone of national critical infrastructures such as power grids, transportation systems, home automation systems, etc. Because cyber-physical systems are widely used in these applications, the security considerations of these systems should be of very high importance. Compromise of these systems in critical infrastructure will cause catastrophic consequences. In this paper, we will investigate the security vulnerabilities of currently deployed/implemented cyber-physical systems. Our analysis will be from a cross-layer perspective, ranging from full cyber-physical systems to the underlying hardware platforms. In addition, security solutions are introduced to aid the implementation of security countermeasures into cyber-physical systems by manufacturers. Through these solutions, we hope to alter the mindset of considering security as an afterthought in CPS development procedures.

Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)

Physically Unclonable Functions (PUFs) were introduced over a decade ago for a variety of security applications. Silicon PUFs exploit uncontrollable random variations from manufacturing to generate unique and random signatures/responses. Existing research on PUFs has focused on either PUF design at the architectural level or optimization of lithography to increase sensitivity to random process variations. However, such sources of randomness may become limited during standard CMOS manufacturing as processes continue to mature especially with the advances in design for manufacturability. In this paper, poly-Si is proposed to improve PUF quality at the materials level. Compared to conventional single crystal Si (sc-Si), defects and trapped charges resulting from the random distribution of crystal grains and grain boundaries (GBs) in poly-Si offer considerable random variations. By using poly-Si only in the PUF region in devices, the randomness of the PUF can be enhanced without impacting other functional circuits and thus the IC yield can be maintained. RO-PUF simulation results based on a poly-Si field effect transistor (FET) model show that compared to sc-Si based PUFs, the reliability of poly-Si based PUFS can be improved from 89.18% to 98.82%.

Reliability vs. security: Challenges and opportunities for developing reliable and secure integrated circuits

As technology further scales, devices offer better performance with faster speed and lower power albeit at the cost of reliability. Advanced technology nodes introduce higher variations in manufacturing processes, and devices experience greater aging and environmental degradation. Although such reliability issues should be suppressed for the sake of performance in both CMOS and post-CMOS devices, researchers have leveraged them for a variety of applications and unique primitives for hardware-oriented security. In this paper, we present a comprehensive study on device reliability and security, and make a qualitative assessment of different variability and degradation sources based on their impact on performance, reliability and security. We conclude that reliability and security both play vital roles for respective applications and must be treated in a holistic manner. Hence we urge the reliability and security communities to work together to develop new technologies for designing high performance, reliable and secure integrated circuits.

Security Beyond CMOS: Fundamentals, Applications, and Roadmap

Hardware-oriented security and trust has traditionally relied on the dominant CMOS technology to develop security primitives and provide protection against different attacks and vulnerabilities. With CMOS nearly reaching its fundamental scaling limit and the shortcomings of current solutions, researchers are now looking to exploit emerging nanoelectronic devices for various security applications. In this paper, we discuss the unique features of three emerging nanoelectronic technologies, namely, phase-change memory, grapheme, and carbon nanotubes, and analyze how these features can aid in hardware security and trust. In addition, we present challenges and future research directions about how to effectively integrate emerging nanoscale devices into hardware security. We emphasize that an interdisciplinary initiative is needed for emerging technologies to reach their full potential in security and trust applications.

Harnessing Nanoscale Device Properties for Hardware Security

Traditional measures for hardware security have heavily relied on currently prevalent CMOS technology. However, with the emergence of new vulnerabilities, attacks and limitations in current solutions, researchers are now looking into exploiting emerging nanoelectronic devices for security applications. In this paper, we discuss three emerging nanoelectronic technologies, namely phase change memory, graphene and carbon nanotubes, to point out some unique features that they offer, and analyze how these features can aid in hardware security. In addition, we present challenges and future research directions for effectively integrating emerging nanoscale devices into hardware security.