Fahmi Elsayed

Efficiency Enhancement of Sigma---Delta Modulator Based Transmitters Using Multi-Level Quantizers

This paper is concerned with the performance of first- and second- order sigma–delta modulator (ΣΔM) based transmitters with an Orthogonal Frequency Division Modulation (OFDM) signal and Code Division Multiplexing Access (CDMA) signal. In particular, the WorldWide Interoperability for Microwave Access (WiMAX) and Interim Standard 95 (IS-95) down link signals have been used for this study as test signals. The simulation and experimental results showed that the performances of the ΣΔM for both signals are improved by increasing the number of quantization levels and the order of the ΣΔM circuit. A ΣΔ modulator based transmitter using a switching mode power amplifier was developed and built for validation purposes. It is found that the increase of the quantization level of the ΣΔ modulator from 2 to 5 leads to a substantial improvement in the measured power efficiency of the transmitter from 5% to 42%. This improvement in efficiency is in good agreement with simulated and measured results obtained using simulink and FPGA board respectively.

Linearized Multi-Level

This paper proposes a new linearization algorithm, discrete level gain adjustment (DLGA), for linearized high efficiency multi-level delta sigma modulator (ΔΣM)-based transmitter architectures adequate for wideband multi-standard software defined radio (SDR) applications. The new simple linearization DLGA algorithm is deployed instead of using a full digitally predistorted to maintain the linearity of the employed switching-mode power amplifier (SMPA) with a considerable decrease in the complexity of the digital signal processing (DSP) unit. The proposed architecture includes a multi-level envelope ΔΣM (EΔΣM) concurrently with a linearized SMPA, in order to achieve a better trade-off of power efficiency versus linearity. Based on DLGA, instead of envelope elimination and restoration (EER) configuration, three-level envelope LPΔΣM-based transmitter in phase elimination and restoration (PER) configuration was implemented. The bandwidth constraint of the EER configuration was relaxed. First, a multi-level Envelope EΔΣM-based transmitter was studied to determine the optimal number of quantizer levels that could be used. Through MATLAB simulation and measurement results, it was shown that the best performance was achieved with a discrete level signal that has three different power levels, including zero and regardless the phase. From the measurements, the linearized three-level PER-LPEΔΣM transmitter shows an efficiency of 36%, signal-to-noise distortion ratio of 43.8 dB and adjacent channel power ratio of 45 dB.

\Delta\Sigma

A new Current Feedback Amplifier (CFA) suitable for VLSI applications is presented in two different designs to serve both low power (LBW design) and high bandwidth (HBW) applications. The new circuit is employing positive current conveyor followed by amplifier followed by buffer to achieve vey high trans-impedance for this CFA circuit without needing to stack many transistors together and at the same time to use the whole bandwidth range. The proposed circuit is designed and simulated using 90nm technology kit in cadence. The bandwidth of the LBW circuit is approximately constant at 32MHz and for HBW is around 107MHz.

Modulated Wireless Transmitters for SDR Applications Using Simple DLGA Algorithm

A new Operational Floating Current Conveyor (OFCC) circuit is presented. The presented OFCC circuit is the first CMOS OFCC circuit which is suitable for low power VLSI applications. The proposed OFCC circuit is designed to achieve two design goals. The first designed circuit is a low power consumption OFCC circuit (LBW design) while the second design is a high bandwidth OFCC circuit (HBW design) with power consumption sacrifice. Both designs are designed and simulated using TSMC 90nm technology kit in Cadence.

A new 90NM CMOS current feedback operational amplifier

This work is concerned with the analysis, based on MATLAB simulation, of 1st and 2nd order Multi-level envelope delta sigma modulators (EDSMs) that are used for high efficiency and linearity wireless mobile transmitter architectures with an Orthogonal Frequency Division Modulation (OFDM) signal and long term evolution (LTE) signal. The analysis is based on measuring the linearity and the efficiency of the three-level EDSM. It was shown that, at different input signal power levels of the three-level EDSM, 1st order three-level EDSM is able to achieve a performance that is close to the performance of the 2nd order counterpart. While 1st order DSM requires less circuitry, it is recommended to employ 1st order three-level EDSM instead of using 2nd order three-level EDSM. 1st order three-level EDSM has a signal to noise distortion ratio (SNDR) and coding efficiency of 58 dB and 77%, respectively. While 2nd order three-level EDSM showed SNDR of 61.5 dB and coding efficiency of 76.4%. Also, with a long term evolution (LTE) signal, the 1st order EDSM has better performance, in terms of SNDR and CE, than that of the 2nd order EDSM circuit.

A CMOS operational floating current conveyor circuit

This paper presents a new electric field array microsystem. The microsystem is fully automated, and it can be used in biomedical applications. The microsystem contains two main parts which are: 1) A CMOS Integrated Circuit (IC) which is based on 0.18 µm technology and includes the sensing and actuation parts, 2) a control circuit board which contains the amplification and conditioning parts. The microsystem is tested in biomedical environment and the experimental results show that the automated microsystem is a suitable candidate for biomedical applications such as: noninvasive biological cell detection, cancer detection and antibody selection.

Performance enhancement of first order three-level envelope delta sigma modulator based transmitter

In this paper, a dual-branch topology driven by a Delta-Sigma Modulator (DSM) with a complex quantizer, also known as the Complex Delta Sigma Modulator (CxDSM), with a 3-level quantized output signal is proposed. By de-multiplexing the 3-level Delta-Sigma-quantized signal into two bi-level streams, an efficiency enhancement over the operational frequency range is achieved. The de-multiplexed signals drive a dual-branch amplification block composed of two switch-mode back-to-back power amplifiers working at peak power. A signal processing technique known as quantization noise reduction with In-band Filtering (QNRIF) is applied to each of the de-multiplexed streams to boost the overall performances; particularly the Adjacent Channel Leakage Ratio (ACLR). After amplification, the two branches are combined using a non-isolated combiner, preserving the efficiency of the transmitter. A comprehensive study on the operation of this topology and signal characteristics used to drive the dual-branch Switch-Mode Power Amplifiers (SMPAs) was established. Moreover, this work proposes a highly efficient design of the amplification block based on a back-to-back power topology performing a dynamic load modulation exploiting the non-overlapping properties of the de-multiplexed Complex DSM signal. For experimental validation, the proposed de-multiplexed 3-level Delta-Sigma topology was implemented on the BEEcube™ platform followed by the back-to-back Class-E switch-mode power amplification block. The full transceiver is assessed using a 4th-Generation mobile communications standard LTE (Long Term Evolution) standard 1.4 MHz signal with a peak to average power ratio (PAPR) of 8 dB. The dual-branch topology exhibited a good linearity and a coding efficiency of the transmitter chain higher than 72% across the band of frequency from 1.8 GHz to 2.7 GHz.

An electric field array microsystem for Lab-on-chip and biomedical analysis

This paper presents a linear high efficiency three-level polar DSM based transmitter that is adequate for wireless RF applications. The polar DSM runs at low sampling frequency that is related to the used oversampling ratio and the bandwidth of the signal standard. Through simulation, a high coding efficiency and high linearity can be achieved concurrently by adjusting the power level of the input signal. A three-level polar DSM was used to drive a switched mode power amplifier to propose a linear high efficiency transmitter that does not need a high sampling frequency. Two quantizers are used in order to preserve the linearity of the transmitter. A sampling frequency of 160 MHz was used for a Worldwide Interoperability for Microwave Access signal has a bandwidth of 1.25 MHz and oversampling ratio of 128. The transmitter has an overall efficiency equal 42% and linearity of 46 dB is achievable with sacrificing a bit of the efficiency.

Three-Level De-Multiplexed Dual-Branch Complex Delta-Sigma Transmitter

This paper presents an electrical field sensor, which can be used in both biomedical applications and cell characterization. The Lab-on-Chip contains two main parts: 1) A CMOS Lab-on-Chip integrated Circuit (IC) which is based on 0.18 µm technology and includes the sensing and actuation parts, 2) a printed circuit board which contains the amplifications and conditioning parts. Experimental result shows that the automated Lab-on-Chip is a good candidate for biomedical applications, such as in the DNA analysis, to detect the radius of the DNA molecule, and in cancer research area, to help in selecting the suitable antibody for cancer treatment.