Wael M. Badawy

A real time vehicle's license plate recognition system

A smart and simple algorithm is presented for a vehicle license plate recognition system. Based on pattern matching, this algorithm can be applied for real time detection of license plates for collecting data for surveying or for some application specific purposes. The proposed system has been prototyped using C++ and the experimental results have been shown for recognition of Alberta license plates.

A novel current-mode instrumentation amplifier based on operational floating current conveyor

This paper presents a novel current-mode instrumentation amplifier (CMIA) that utilizes an operational floating current conveyor (OFCC) as a basic building block. The OFCC, as a current-mode device, shows flexible properties with respect to other current- or voltage-mode circuits. The advantages of the proposed CMIA are threefold. First, it offers a higher differential gain and a bandwidth that is independent of gain, unlike a traditional voltage-mode instrumentation amplifier. Second, it maintains a high common-mode rejection ratio (CMRR) without requiring matched resistors, and finally, the proposed CMIA circuit offers a significant improvement in accuracy compared to other current-mode instrumentation amplifiers based on the current conveyor. The proposed CMIA has been analyzed, simulated, and experimentally tested. The experimental results verify that the proposed CMIA outperforms existing CMIAs in terms of the number of basic building blocks used, differential gain, and CMRR.

Video-Based Automatic Incident Detection for Smart Roads: The Outdoor Environmental Challenges Regarding False Alarms

Video-based automatic incident detection (AID) systems are increasingly being used in intelligent transportation systems (ITS). Video-based AID is a promising method of incident detection. However, the accuracy of video-based AID is heavily affected by environmental factors such as shadows, snow, rain, and glare. This paper presents a review of the different work done in the literature to detect outdoor environmental factors, namely, static shadows, snow, rain, and glare. Once these environmental conditions are detected, they can be compensated for, and hence, the accuracy of alarms detected by video-based AID systems will be enhanced. Based on the presented review, this paper will highlight potential research directions to address gaps that currently exist in detecting outdoor environmental conditions. This will lead to an overall enhancement in the reliability of video-based AID systems and, hence, pave the road for more usage of these systems in the future. Last, this paper suggests new contributions in the form of new suggested algorithmic ideas to detect environmental factors that affect AID systems accuracy.

Sensing methods for dielectrophoresis phenomenon: from bulky instruments to lab-on-a-chip

Recently, the sensing methods for dielectrophoresis (DEP) have been changed from bulky instruments to lab-on-a-chip. Lab-on-a-chip based the dielectrophoresis phenomenon holds the promise to give biology the advantage of miniaturization for carrying out complex experiments. However, until now, there is an unmet need for lab-on-a-chip to effectively deal with the biological systems at the cell level.

Efficient distributed arithmetic based DWT architecture for multimedia applications

This paper presents a novel architecture for 9/ Discrete Wavelet Transform (DWT) based on Distributed Arithmetic (DA). The proposed architecture optimizes the performance by exploiting the computational redundancy. The DWT inner product of coefficient matrix is distributed over the input by careful analysis of input, output and coefficients word lengths. In the coefficient matrix, linear maps are used to assign the necessary computation processing elements in space domain. The result is a low hardware complexity DWT processor for 9/7 transforms, which allows two times faster clock than the direct implementation. In the proposed architecture reducing the clock frequency by two or the supply voltage and maintaining the same throughput as of other architecture achieve the low power by a factor of four. The proposed architecture is therefore scalable and can operate at high speed / consumes low power and has reduced computational complexity (improvement of 77.6% over filter based and 40.27% over lifted based architectures) as compared to already published 9/7 biorthogonal wavelet architectures.

CAVLC Encoder Design for Real-Time Mobile Video Applications

This brief presents a new context-based adaptive variable length coding (CAVLC) architecture. The prototype is designed for the H.264/AVC baseline profile entropy coder. The proposed design offers area savings by reducing the size of the statistic buffer. The arithmetic table elimination technique further reduces the area. The split VLC tables simplify the process of bit-stream generation and also help in reducing some area. The proposed architecture is implemented on Xilinx Virtex II field-programmable gate array (2v3000fg676-4). Simulation result shows that the architecture is capable of processing common/quarter-common intermediate format frame sequences in real-time at a core speed of 50 MHz with 6.85-K logic gates.

UMHexagonS algorithm based motion estimation architecture for H.264/AVC

This paper presents an integer pel variable block motion estimation architecture based on JVT accepted UMHexagonS algorithm for H.264/MPEG-4 part 10 (AVC) encoder. The proposed pipelined architecture is capable of calculating the required 41 motion vectors of various size blocks supported by H.264/AVC within a 16/spl times/16 block in parallel. The architecture can be used for rapid prototyping of motion estimation core using FPGA. The performance analysis shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of /spl plusmn/16 at a clock speed of around 30 MHz.

Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC)

The paper presents a VLSI prototype for context-based adaptive variable length coding (CAVLC). This scheme is a part of the lossless compression process in the MPEG-4 Part 10 standard. It is applied to the quantized transform coefficients of the luminance component during the entropy coding process. In combination with previous transformations and quantizations, it can result in significantly increased compression ratio. The developed architecture is prototyped and simulated using ModelSim 5.4/spl reg/. It is synthesized using Synplify Pro 7.1/spl reg/. The results show that the architecture satisfies the real-time constraints required by different digital video applications.

Algorithm-based low-power VLSI architecture for 2D mesh video-object motion tracking

The new VLSI architecture for video object (VO) motion tracking uses a novel hierarchical adaptive structured mesh topology. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the VO. Motion compensation is performed using a multiplication-free algorithm for affine transformation, significantly reducing the decoder architecture complexity. Pipelining the affine unit contributes a considerable power saving. The VO motion-tracking architecture is based on a new algorithm. It consists of two main parts: a video object motion-estimation unit (VOME) and a video object motion-compensation unit (VOMC). The VOME processes two consequent frames to generate a hierarchical adaptive structured mesh and the motion vectors of the mesh nodes. It implements parallel block matching motion-estimation units to optimize the latency. The VOMC processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion-compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. Performance analysis shows that this processor can be used in online object-based video applications such as MPEG-4 and VRML.

A new topology for a current-mode wheatstone bridge

This paper presents a new topology for a current-mode Wheatstone bridge (CMWB) that uses an operational floating current conveyor (OFCC) as a basic building block. The proposed CMWB has been analyzed, simulated, implemented, and experimentally tested. The experimental results verify that the proposed CMWB outperforms existing CMWBs in terms of accuracy. A new CMWB linearization technique based on OFCC has been proposed, used, analyzed, and tested. The advantages of the proposed CMWB are fourfold. Firstly, it reduces the number of sensing passive elements; i.e., we can use two resistors instead of four and get the same performance as the traditional voltage-mode implementation. Secondly, we can apply the superposition principle without adding signal conditioning circuitry; therefore, the addition of sensor effects is possible. Thirdly, it has a higher common-mode cancellation. Finally, the proposed CMWB topology offers a significant improvement in accuracy compared to other CMWBs