Falah Awwad

Transcriptome Analysis Reveals Genes Commonly Induced by Botrytis cinerea Infection, Cold, Drought and Oxidative Stresses in Arabidopsis

Signaling pathways controlling biotic and abiotic stress responses may interact synergistically or antagonistically. To identify the similarities and differences among responses to diverse stresses, we analyzed previously published microarray data on the transcriptomic responses of Arabidopsis to infection with Botrytis cinerea (a biotic stress), and to cold, drought, and oxidative stresses (abiotic stresses). Our analyses showed that at early stages after B. cinerea inoculation, 1498 genes were up-regulated (B. cinerea up-regulated genes; BUGs) and 1138 genes were down-regulated (B. cinerea down-regulated genes; BDGs). We showed a unique program of gene expression was activated in response each biotic and abiotic stress, but that some genes were similarly induced or repressed by all of the tested stresses. Of the identified BUGs, 25%, 6% and 12% were also induced by cold, drought and oxidative stress, respectively; whereas 33%, 7% and 5.5% of the BDGs were also down-regulated by the same abiotic stresses. Coexpression and protein-protein interaction network analyses revealed a dynamic range in the expression levels of genes encoding regulatory proteins. Analysis of gene expression in response to electrophilic oxylipins suggested that these compounds are involved in mediating responses to B. cinerea infection and abiotic stress through TGA transcription factors. Our results suggest an overlap among genes involved in the responses to biotic and abiotic stresses in Arabidopsis. Changes in the transcript levels of genes encoding components of the cyclopentenone signaling pathway in response to biotic and abiotic stresses suggest that the oxylipin signal transduction pathway plays a role in plant defense. Identifying genes that are commonly expressed in response to environmental stresses, and further analyzing the functions of their encoded products, will increase our understanding of the plant stress response. This information could identify targets for genetic modification to improve plant resistance to multiple stresses.

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments were used in the transfer function, as opposed to previous Elmore delay models which consider only one moment for RC interconnects. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using a 0.25-mum CMOS technology. Simulation results show that this repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide VLSI/SoC designers with optimal design parameters, such as the type as well as the position and size of repeaters to be used for interconnect regeneration, faster than with conventional HSpice simulations.

Modified null convention logic pipeline to detect soft errors in both null and data phases

Glitches due to soft errors can act as a severe deterrent to asynchronous circuit operations. To mitigate soft errors in quasi delay insensitive (QDI) asynchronous circuits, built-in soft error correction in NULL convention logic (NCL) has been introduced [9]. However, this technique cannot detect errors during the NULL phase of NCL pipeline, and also cannot avoid error propagation into the pipeline after its detection. This paper provides a modified approach to overcome these limitations with, on average, comparable power and latency costs. This work also analyzes the temperature variation effects on latency and power consumption of the proposed design. The modified NCL pipeline is implemented in IHP 90nm CMOS technology and analyzed under various operating temperatures. It is found that the proposed design survives well in the worst case operating temperatures and does not propagate soft errors.

A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications

In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents.

Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline

Glitches due to soft errors have become a major concern in circuits designed in ultra-deep sub-micron technologies. Most of the soft error mitigation techniques require redundancy and are power hungry. Recently, low power quasi delay insensitive (QDI) null conventional logic based asynchronous circuits have been proposed, but these circuits work for pure asynchronous designs only. This paper extends the low-power soft-error-tolerant asynchronous technique for conventional synchronous circuits. The main idea is to accommodate asynchronous standard cells within the synchronous pipeline, and thus giving rise to a macro synchronous micro asynchronous (MSMA) pipeline. An important application of this design is found in detecting the hardware Trojans. The state-of-the-art signature based hardware Trojan detection is implemented using the clock referencing signals for timing signatures. However, an intruder can intrude into clock distribution network itself and may lead to many false positive or even false negative cases. Asynchronous handshake signals, on the other hand, provide event trigger nature to the digital system, and hence the timing analysis is unique to the data path itself alone, without getting affected by the clock distribution network. This paper provides a proof of concept soft error tolerant MSMA design. Time delay based signature without using clock distribution network is obtained to detect hardware Trojan insertion in MSMA.

Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs

Hardware security is a major concern in the intellectual property (IP) centric integrated circuits (IC). 3-D IC design augments IP centric designs. However, 3-D ICs suffer from high temperatures in their middle tiers due to long heat dissipation paths. We anticipate that this problem would exacerbate the hardware security issues in 3-D ICs. Because, high temperature leads to undesired timing characteristics in ICs. In this paper we provide a detailed analysis on how these delay variations can lead to non-ideal behavior of control paths. It is demonstrated that a hardware intruder can leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. Our simulation results show that a state machine can lead to temporary glitches long enough to cause malfunctioning at temperatures of 87°C or above, under nominal frequencies. The overall area overhead of the payload compared to a very small Mod-3 counter is 6%.

TBCD-TDM: Novel Ultra-Low Energy Protocol for Implantable Wireless Body Sensor Networks

The field of Remote health monitoring now includes technologies such as home and mobile health monitoring, tele-retinal imaging, tele-radiology, remote cardiac monitoring, video conferencing and sensors for remote diagnosis and treatment to patients. In this regard, implantable wireless body sensor networks (IWBSNs) have recently emerged as an important and growing research area. These implantable sensors are required to be reliable, very small, battery-operated, and capable of collecting data, processing it, and transmitting it wirelessly and efficiently. Since these devices are required to run with limited resources (energy, processing, and memory), their utility protocols (collecting, processing, and communication) should be designed carefully, not only to work reliably but, more importantly, to be resource-efficient. The life time of the embedded batteries associated with these sensor nodes varies from a few days to a few weeks as was described in a previous work by the authors. In this paper, we propose a novel technique which allows the implanted sensor nodes to communicate with a base station located outside the body efficiently by consuming the minimum amount of energy. Our proposed protocol allows the battery to last significantly longer even for years with a gain of up to 100s times of power saving. This will improve the quality of patient life, and reduce risk of infection resulting from frequent chirurgical operations needed to replace such implantable batteries. Also, a new time synchronization algorithm is briefly introduced in this work that is especially applicable to our proposed communication protocol.

Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline

Advancement in deep submicron (DSM) technologies led to miniaturization. However, it also increased the vulnerability against some electrical and device non-idealities, including the soft errors. These errors are significant threat to the reliable functionality of digital circuits. Several techniques for the detection and deterrence of soft errors (to improve the reliability) have been proposed, both in synchronous and asynchronous domain. In this paper we propose a low power and soft error tolerant solution for synchronous systems that leverages the asynchronous pipeline within a synchronous framework. We named our technique as macro synchronous micro asynchronous (MSMA) pipeline. We provided a framework along with timing analysis of the MSMA technique. MSMA is implemented using a macro synchronous system and soft error tolerant and low power version of null convention logic (NCL) asynchronous circuit. It is found out that this solution can easily replace the intermediate stages of synchronous and asynchronous pipelines without changing its interface protocol. Such NCL asynchronous circuits can be used as a standard cell in the synchronous ASIC design flow. Power and performance analysis is done using electrical simulations, which shows that this techniques consumes at least 22% less power and 45% less energy delay product (EDP) compared to state-of-the-art solutions.

Parallel Implementation and Performance Analysis of a 3D Oil Reservoir Data Visualization Tool on the Cell Broadband Engine and CUDA GPU

Usefulness of graphically visualizing and manipulating large data sets in oil and gas exploration and production is as important as ever. This paper describes the development and parallelization of a multi-phase 3D oil-water reservoir visualization tool on the IBM Cell computer and CUDA enabled GPU. An independent Oil reservoir simulator described in [1] was used to generate the pressure and oil / water saturation values over a certain period of time. The oil reservoir visualization tool displays data grids in a 3D environment and allows the user to interact with it. Due to large speed requirements, our aim is to parallelize the computations required to interact with and visualize the grid, mainly transformation [2], zooming, camera movement [3] and compute intensive lighting model [4][5]. This tool also allows the user to playback the simulation results over a time duration and fetches data values upon mouse click at a particular grid point on a particular day. The development environments are nVIDIA CUDA and IBM Cell SDK 3.0 along with QT and OpenGL libraries. Various experiments were run on an ×86 computer with nVIDIA Quadro FX 5800 GPU, and on an IBM Cell BE computer with 1 QS20 Cell blade containing two 9-core Cell processor packages. Our results indicate that the nVIDIA GPU provides on average, speed up of 67× over serial implementation and IBM Cell BE with 16 SPE SIMD implementation 32× over the serial implementation.

Regeneration techniques for RLC VLSI interconnects

On-chip inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 /spl mu/m TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% area-delay product saving over the serial regeneration.