Syed Rafay Hasan

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Abstract Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.

New Insights Into the Single Event Transient Propagation Through Static and TSPC Logic

An investigation of the Single Event Transient (SET) characteristics (amplitude and width) variation while propagating through static and True Single Phase Clock (TSPC) logic is presented. The dependencies of the SET characteristics on the input patterns, propagation paths, pulse polarity, diverging paths, and re-converging paths are investigated. New insights on the propagation induced pulse broadening (PIPB) phenomenon in different combinations of static and TSPC logic are reported. The worst and the best propagation paths for SET pulse broadening and attenuation are identified. Our results demonstrate that SET pulses propagation can lead to Byzantine faults as they propagate through diverging paths. A new way to abstract all possible interpretations of the SET induced Byzantine fault phenomenon is proposed.

Modified null convention logic pipeline to detect soft errors in both null and data phases

Glitches due to soft errors can act as a severe deterrent to asynchronous circuit operations. To mitigate soft errors in quasi delay insensitive (QDI) asynchronous circuits, built-in soft error correction in NULL convention logic (NCL) has been introduced [9]. However, this technique cannot detect errors during the NULL phase of NCL pipeline, and also cannot avoid error propagation into the pipeline after its detection. This paper provides a modified approach to overcome these limitations with, on average, comparable power and latency costs. This work also analyzes the temperature variation effects on latency and power consumption of the proposed design. The modified NCL pipeline is implemented in IHP 90nm CMOS technology and analyzed under various operating temperatures. It is found that the proposed design survives well in the worst case operating temperatures and does not propagate soft errors.

Quantitative analysis of State-of-the-Art synchronizers: Clock domain crossing perspective

Reliable transferring of data from one clock domain to another requires synchronization. Therefore, synchronizers play an important role in clock domain crossing (CDC). But despite their wide applications, there is no standard quantitative metric available to analyze various synchronizer configurations on common grounds. To overcome this limitation, this paper presents a comparison of three basic and widely used synchronizers. Latency and power consumption metric are measured for level, edge-detecting and pulse generating synchronizers. Furthermore, effects of these synchronizers are studied when applied to some commonly used asynchronous handshaking protocols under 90nm CMOS technology.

Modeling, analyzing, and abstracting single event transient propagation at gate level

Soft errors have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. A new methodology to abstract, model, and analyze Single Event Transient (SET) propagation at different abstraction levels (transistor and gate level) is proposed. Transistor level characterization libraries are developed to abstract the impact of input patterns, pulse polarity, and propagation paths characteristics on the SET duration. Thereafter, these libraries are utilized to analyze SET pulse propagation at gate level using MDG model checker. We have implemented the proposed method on different ISCAS85 benchmark combinational circuits. The proposed methodology is orders of magnitude faster than circuit level simulations. Moreover, we have developed gate level characterization libraries to abstract SET pulse propagation behavior at the gate level.

Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline

Glitches due to soft errors have become a major concern in circuits designed in ultra-deep sub-micron technologies. Most of the soft error mitigation techniques require redundancy and are power hungry. Recently, low power quasi delay insensitive (QDI) null conventional logic based asynchronous circuits have been proposed, but these circuits work for pure asynchronous designs only. This paper extends the low-power soft-error-tolerant asynchronous technique for conventional synchronous circuits. The main idea is to accommodate asynchronous standard cells within the synchronous pipeline, and thus giving rise to a macro synchronous micro asynchronous (MSMA) pipeline. An important application of this design is found in detecting the hardware Trojans. The state-of-the-art signature based hardware Trojan detection is implemented using the clock referencing signals for timing signatures. However, an intruder can intrude into clock distribution network itself and may lead to many false positive or even false negative cases. Asynchronous handshake signals, on the other hand, provide event trigger nature to the digital system, and hence the timing analysis is unique to the data path itself alone, without getting affected by the clock distribution network. This paper provides a proof of concept soft error tolerant MSMA design. Time delay based signature without using clock distribution network is obtained to detect hardware Trojan insertion in MSMA.

Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems

This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits.

Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs

Hardware security is a major concern in the intellectual property (IP) centric integrated circuits (IC). 3-D IC design augments IP centric designs. However, 3-D ICs suffer from high temperatures in their middle tiers due to long heat dissipation paths. We anticipate that this problem would exacerbate the hardware security issues in 3-D ICs. Because, high temperature leads to undesired timing characteristics in ICs. In this paper we provide a detailed analysis on how these delay variations can lead to non-ideal behavior of control paths. It is demonstrated that a hardware intruder can leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. Our simulation results show that a state machine can lead to temporary glitches long enough to cause malfunctioning at temperatures of 87°C or above, under nominal frequencies. The overall area overhead of the payload compared to a very small Mod-3 counter is 6%.

Design constraints of a hypertransport-compatible network-on-chip

Hypertransport (HT) is an emerging system integration communication technology. There is a need for a network on chip (NOC) technology compatible with this cutting-edge system technology. This paper reveals design constraints involved in implementing an HT-compatible NOC. In order to provide a simple and HT-compatible solution, we propose an architecture called hypertransport super lite (HTSL). The new architecture allows a reduction of more than 14 times in required buffer space, while keeping the functionality unaffected. Moreover, exploiting the advantages of on-chip architecture leverages the processing complexity of each node in the architecture.

Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline

Advancement in deep submicron (DSM) technologies led to miniaturization. However, it also increased the vulnerability against some electrical and device non-idealities, including the soft errors. These errors are significant threat to the reliable functionality of digital circuits. Several techniques for the detection and deterrence of soft errors (to improve the reliability) have been proposed, both in synchronous and asynchronous domain. In this paper we propose a low power and soft error tolerant solution for synchronous systems that leverages the asynchronous pipeline within a synchronous framework. We named our technique as macro synchronous micro asynchronous (MSMA) pipeline. We provided a framework along with timing analysis of the MSMA technique. MSMA is implemented using a macro synchronous system and soft error tolerant and low power version of null convention logic (NCL) asynchronous circuit. It is found out that this solution can easily replace the intermediate stages of synchronous and asynchronous pipelines without changing its interface protocol. Such NCL asynchronous circuits can be used as a standard cell in the synchronous ASIC design flow. Power and performance analysis is done using electrical simulations, which shows that this techniques consumes at least 22% less power and 45% less energy delay product (EDP) compared to state-of-the-art solutions.