Fan Xiangning

Improvement on LEACH Protocol of Wireless Sensor Network

This paper studies LEACH protocol, and puts forward energy-LEACH and multihop-LEACH protocols. Energy-LEACH protocol improves the choice method of the cluster head, makes some nodes which have more residual energy as cluster heads in next round. Multihop-LEACH protocol improves communication mode from single hop to multi-hop between cluster head and sink. Simulation results show that energy-LEACH and multihop-LEACH protocols have better performance than LEACH protocols.

An improved channel estimation algorithm for OFDM UWB

Channel estimation is very important for OFDM based UWB system because of its coherent demodulation. In this paper, a new improved channel estimation method is proposed based on the characteristics of the UWB channels. Compare with the estimator using discrete Fourier-transform, the proposed algorithm can properly choose suitable length of time-domain filter by distinguishing different channel conditions. It is shown by simulation that better performance can be achieved especially for IEEE cm1 and cm2 channels.

An improved low phase noise and low power consumption VCO for WSN applications

A 4.8GHz low phase noise and low power consumption LC voltage controlled oscillator (VCO) used in frequency synthesizer for Wireless Sensor Network (WSN) applications is designed and implemented based on TSMC 0.18μm RF CMOS process. Complementary differential negative resistance LC oscillator structure is adopted to achieve low power consumption. The core circuit is biased by current so as to reduce sensitivity to power supply and to further decrease power consumption. LC tank is carefully designed to lower phase noise. A 3 bit switch capacitor array provides large tuning range without worsen the phase noise performance. The output buffer of common source structure is adopted because of its decent reverse isolation. With a 1.8V supply voltage, measurement results show that the whole tuning range achieves 20% which can perfectly compensates the deviation due to power supply, process corners and temperature. The phase noise of-121.41dBc/Hz is obtained at 3MHz offset with the carrier of 4.8GHz. The chip size is 700μm×900μm and the operating current of core circuit is only 1.5mA.

CMOS Phase Frequency Detector and Charge Pump for Wireless Sensor Networks

As the key blocks of PLL (phase locked loop) circuits, PFD (Phase Frequency Detector) is dominated to the precision and stability of system, whereas CP (Charge Pump) offers a wide scale of frequency capture scale and fast locked performance. The structure of PFD using transfer gate dynamic D flip-flops and the structure with a wide input scale error amplifier for CP had been presented to achieve a high performance. In the end, the chip was taped out in the process of TSMC 0.18μm CMOS. The post-simulation results show that the PFD has correct logic function, whereas the charge pump current is stable at 100μA in the output range of 0.2V~0.8V, and the current mismatch is less than 0.4μA at output voltage range of 0.2V~0.8V, with total power consumption of 3mW with the power supply of 1V.

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a −1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured IIP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

An efficient CMOS DC offset cancellation circuit for PGA of low IF wireless receivers

In this paper, the sources of DC offset in the front-ends of wireless systems are discussed and corresponding DC offset cancellation techniques are analyzed. Upon the discussion, a DC negative feedback technique based DC offset canceller, which is concise and easy to be integrated on chip, is elaborated in details by SMIC 0.18μηι CMOS process. DC offset detector is an integral part of DC offset canceller. In this paper, an on chip DC offset detection circuit is proposed for the DC negative feedback canceller which can be used in the CMOS programmable gain amplifier (PGA) of a low intermediate frequency (IF) receiver as which in IEEE802.15.4/ZigBee wireless sensor network. Post-simulation and chip measurement results show that the DC offset canceller performs well.

A wideband LC-VCO with small VCO gain variation and adaptive power control

A wideband LC tank voltage-controlled-oscillator (VCO) is proposed. To solve the impacts of wideband operation on VCO gain (KVCO) variation and start-up constraint, a binary-weighted varactor array and a binary-weighted negative resistance array all with optimal unit values are designed. Implemented in a 0.18 μm CMOS process, the proposed VCO shows a frequency tuning range from 1.9 to 3.1 GHz, with a current consumption varying accordingly from 14.2 to 4 mA from a 1.8 V supply. With the proposed KVCO suppression technique, the KVCO varies from 50 to 60 MHz/V in the entire frequency range. The measured phase noise is −117 dBc/Hz at a 1 MHz offset from a 3 GHz carrier.

Analysis and Comparison of Different SC-FDMA Schemes for 3GPP LTE

Single-carrier FDMA (SC-FDMA) is a new kind of FDMA system which was proposed in recent years. It has the same PAPR as single-carrier system and its resource scheduling is as flexible as multi-carrier system. For comparison, the 3GPP LTE uplink scheme DFT-S-OFDM, and our new scheme DFT-S-GMC which is based on DFT and General Multi-Carrier (GMQ are analyzed and discussed in detail. Analysis and simulation results show that DFT-S-GMC is better than DFT-S-OFDM in Multiple Address Interference (MAI) performance. And the complexity of DFT-S-GMC is also reduced by using multi-band filter-banks.

Implementation of an improved active CMOS mixer with high linearity for wideband wireless systems

This paper designs and implements an direct up-conversion mixer based on RF CMOS process, which can be used in the up-link radio frequency (RF) front-end of a 2.4GHz wideband wireless system such as multimedia wireless sensor network (WSN). Firstly, Gilbert cell-based double-balanced structure is adopted in this design, which can effectively suppress the feed-through of the local oscillator (LO) signal to the RF port, and as well as that of the intermediate frequency (IF) signal to the RF port. Then, an improved Gilbert cell structure-based circuit is proposed by introducing source degeneration technique to improve the linearity of the up-mixer. LC resonant network is used as load of the mixer to select the first-order mixing items. Finally, the mixer is fabricated in TSMC 0.18μm 1P6M RF CMOS process. Measured results show that the mixer performs well and has better linearity, the input 1dB compression point is −1dBm, and the conversion gain is −0.5dB with the total current (including the mixer core and the buffer) of 16mA. The entire chip area (including the pads) is 780μm×560μm.

A 2.4-GHz CMOS up-conversion mixer for WSN SoC applications

Mixer is one of the main modules of a transmitter system, and its performance will heavily impact the functionality of the entire transmitter. Gilbert cell structure can achieve high degree of RF (Radio Frequency) and LO (Local Oscillator) isolation, thus loosening filtering output requirements. This design employs a resonant LC network as the load to improve gain, increase the output voltage swing, and inhibit the high-order harmonic generation. It uses feedback to improve the linearity of the mixer. The current-reuse bleeding double-balanced mixer operates at 2.4GHz. And the up-conversion mixer uses an intermediate frequency (IF) input frequency of 1.2MHz, a local oscillator (LO) of frequency 2.4GHz and a RF output frequency of 2.4012GHz. Experimental test chip is realized. Measured results demonstrate −2.01dB conversion gain, and −13dBm input compression point with 11.9mA total current with a 1.8V supply. The current in Gilbert Cell is 2.9mA and the current in buffer is 9mA.