Wang Zhigong

Study of microelectronics for detecting and stimulating of central neural signals

Test circuits for the signal detection and the function electrical stimulation (FES) of neurons have been designed, implemented at first by using discrete devices and characterized off-body. The detecting circuit consisting of three-stage operational amplifiers has a controllable gain up to 10/sup 5/, a -3 dB bandwidth of 30 kHz, and an equivalent input noise of about 9 nV//spl radic/Hz. The FES circuit consisting of two-stage operational amplifiers has a bandwidth of more than 10 kHz and a variable gain from 20 dB to 60 dB can provide a current of more than 1 mA to a load of 10 k/spl Omega/ They are intended to connect with both cuff-type and staff-type microelectrodes. Integrated circuits (IC) for the neural signal process have been designed with features of low voltage and low power. A more biocompatible composite has been synthesized to modify the silicon and related material.

Optimized design for high-speed parallel BCH encoder

A new design method for parallel BCH encoder is presented, which can eliminate the bottleneck in long BCH encoder. Based on serial LFSR architecture, a recursive formula which can deduce the parallel BCH encoder was first derived. The complexity and the delay of the critical paths of the circuit could be effectively decreased by using a tree-type structure, sharing sub-expression and limiting its maximum number, and balancing load technique. Finally, a parallel BCH (2184, 2040) encoder with 8-bit parallelism is realized in TSMCs 0.18 /spl mu/m CMOS technology for high-speed optical communication that can operate at 400 MHz and process data at the rate of 2.5 Gb/s.

A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area.

Design techniques of CMOS SCL circuits for Gb/s applications

This paper presents the design techniques of Gb/s CMOS SCL circuits. Basic SCL functional cells including a 2:1 multiplexer, a D-latch, and XOR/NXOR, AND/NAND, OR/NOR gates are described in detail. Simulations show that a SCL static frequency divider can operate faster than a CMOS static logic one. Experimental results of an SCL 1:4 static frequency divider and an SCL 4:1 multiplexer both in 0.35 /spl mu/m CMOS technology prove that SCL circuits can be used in Gb/s applications.

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of −15 dBm.

A multichannel neural signal detecting module： Its design and test in animal experiments

Abstract A four-channel neural signal detecting module with an implantable 12-contact cuff electrode was designed for real-time neural signal recording on peripheral and central nerves. The mathematic coupling model between nerve and electronic system was analyzed. Electrode connection configurations were considered. The detecting circuit included an input coupling network, a pre-amplifier, and some filtering and notching stages. Shield guarding and the right-leg-driven circuit were developed for further climination of common mode interference. By electrode switches, the module could cooperate with a nerve functional electrical stimulation circuit, building a neural channel bridge-connection system. It was tested by recording experiments on rats sciatic and spine nerves. The signals is spontaneous and evoked conditions have been captured successfully. In addition, an implantable neural signal detecting CMOS IC has been introduced. *Supported by National Natural Science Foundation of China (Grant Nos. 698...

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a −1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured IIP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

Design and analysis of a three-stage voltage-controlled ring oscillator

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator (ring VCO) based on a different cascade voltage logic delay cell with current-source load to change the current of output node. The method for optimization is presented. Furthermore, the analysis of performance of the proposed ring VCO is confirmed by the measurement results. The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC. The measurement results show that the oscillator frequency of the ring VCO is from 0.770 to 5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of 15.1 mW from a 1.8 V supply while occupying only 0.00175 mm2 of the core die area.

A wideband LC-VCO with small VCO gain variation and adaptive power control

A wideband LC tank voltage-controlled-oscillator (VCO) is proposed. To solve the impacts of wideband operation on VCO gain (KVCO) variation and start-up constraint, a binary-weighted varactor array and a binary-weighted negative resistance array all with optimal unit values are designed. Implemented in a 0.18 μm CMOS process, the proposed VCO shows a frequency tuning range from 1.9 to 3.1 GHz, with a current consumption varying accordingly from 14.2 to 4 mA from a 1.8 V supply. With the proposed KVCO suppression technique, the KVCO varies from 50 to 60 MHz/V in the entire frequency range. The measured phase noise is −117 dBc/Hz at a 1 MHz offset from a 3 GHz carrier.

A wide tuning range LC-VCO using switched capacitor array technique

A 2.4GHz low phase noise CMOS LC voltage-controlled oscillator (VCO) is presented. By using a novel three-bit binary-weighted switched capacitor array, the VCO achieves a tuning range of 51.7% from 1.70GHz to 2.94GHz. Designed in SMIC 0.18-μm CMOS technology, the proposed VCO occupies a size of 500μm×700μm. The VCO achieves a phase noise of −123.8dBc/Hz at 1MHz offset from the carrier frequency of 2.4GHz and draws 8.4mA current from 1.8V supply.