Fan Ye

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches (DTMOS), an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide (BOX). The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide (eox) than that of Si (eSi). Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF (reduced surface field) effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit (HVIC), effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

A low specific on-resistance (Ron, sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features:a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron, sp. Second, in the y-direction, the BOXs electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron, sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron, sp by 80% at the same BV.

Ultra-low specific on-resistance vertical double-diffused metal - Oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench (HK TG VDMOS) is proposed in this paper. The HK TG VDMOS features a high-k (HK) trench below the trench gate. Firstly, the extended HK trench not only causes an assistant depletion of the n-drift region, but also optimizes the electric field, which therefore reduces Ron,sp and increases the breakdown voltage (BV). Secondly, the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration. Thirdly, compared with the superjunction (SJ) vertical double-diffused metal-oxide semiconductor (VDMOS), the new device is simplified in fabrication by etching and filling the extended trench. The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩcm2 is obtained by simulation; its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%, in comparison with those of the conventional trench gate VDMOS (TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce Ron,sp and maintain a high breakdown voltage (BV). The BV of 233 V and Ron,sp of 4.151 mΩcm2 (VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.