Luo Xiaorong

A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench

A novel silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) with a high figure of merit (FOM) is proposed. The device features a double-sided charge oxide-trench (DCT) and a trench gate extended to the buried oxide. First, the oxide trench causes multiple-dimensional depletion in the drift region, which not only improves the electric field (E-field) strength, but also enhances the reduced surface field effect. Second, self-adaptive charges are collected in the DCT, which enhances the E-field strength of the trench oxide. Third, the oxide trench folds the drift region along the vertical direction, reducing the device cell pitch. Fourth, one side of the DCT regions acts as the body contact of p-well to reduce cell pitch and specific on-resistance (Ron,sp) further. Compared with a trench gate lateral double-diffused MOSFET, the DCT MOSFET increases the breakdown voltage (BV) from 53 V to 158 V at the same cell pitch of 3.5 μm, or reduces the cell pitch by 60% and Ron,sp by 70% at the same BV. The FOM (FOM=BV2/Ron,sp) of the proposed structure is 23 MW/cm2.

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (Ron,sp) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and Ron,sp of 0.985 mΩ·cm2 (VGS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, Ron,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩcm2 to 36.6 mΩcm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

An ultra-low specific on-resistance (Ron,sp) oxide trench-type silicon-on-insulator (SOI) lateral double-diffusion metal–oxide semiconductor (LDMOS) with an enhanced breakdown voltage (BV) is proposed and investigated by simulation. There are two key features in the proposed device: one is a U-shaped gate around the oxide trench, which extends from source to drain (UG LDMOS); the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field (E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 mΩ·cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS (CT LDMOS), realizing the state-of-the-art trade-off between BV and Ron,sp.

High-voltage super-junction lateral double-diffused metal—oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal—oxide semiconductor (SJ-LDMOS) with a partial lightly doped P pillar (PD) is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P− junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage (BV). In addition, due to the same conduction paths, the specific on-resistance (Ron,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 m??cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,Sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF (T-resurf) SOI LDMOS structure is proposed. This structure has a P-type buried layer. Firstly, the depletion layer can extend on both sides of the P-buried layer, serving as a triple RESURF and leading to a high drift doping and a low on-resistance. Secondly, at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side, which results in uniform bulk electric field distributions and an enhanced BV. The proposed structure is used in SOI devices for the first time. The T-resurf SOI LDMOS with BV D 315 V is obtained by simulation on a 6 m-thick SOI layer over a 2 m-thick buried oxide layer, and its Rsp is reduced from 16.5 to 13.8 mcm 2 in comparison with the double RESURF (D-resurf) SOI LDMOS. When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV 2 /Ron. It reduces Rsp by 25% in 400 V SOI LDMOS and by 38% in 550 V SOI LDMOS compared with the D-resurf structure.

A Low Specific on-Resistance SOI Trench MOSFET with a Non-Depleted Embedded p-Island

A novel silicon-on-insulator (SOI) trench metal-oxide-semiconductor field effect transistor (MOSFET) with a reduced specific on-resistance (Ron,sp) is presented. It features an oxide-filled trench and a non-depleted embedded p-type island (p-SOI). The oxide trench folds the drift region into a U-shape, resulting in a reduction in cell pitch and Ron,sp. The non-depleted p-island is employed to further reduce Ron,sp by increasing the optimized doping concentration of the drift region without deteriorating the breakdown voltage (BV). The simulation results show that the p-SOI decreases the Ron,sp to 10.2mΩcm2 from 17.4mΩcm2 of the conventional SOI MOSFET at the same BV.

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator (SOI) power lateral MOSFET with a dual vertical field plate (VFP) in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, which enhances the internal field of the drift region and increases the drift doping concentration of the drift region, resulting in remarkable improvements in breakdown voltage (BV) and specific on-resistance (Ron,sp). The mechanism of the VFP is analyzed and the characteristics of BV and Ron,sp are discussed. It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V, and the Ron,sp decreases from 366 mΩcm2 to 110 mΩcm2.

Novel SOI double-gate MOSFET with a P-type buried layer

An ultra-low specific on-resistance (Ron,sp) integrated silicon-on-insulator (SOI) double-gate triple RESURF (reduced surface field) n-type MOSFET (DG T-RESURF) is proposed. The MOSFET features two structures: an integrated double gates structure (DG) that combines a planar gate with an extended trench gate, and a p-type buried layer (BP) in the n-type drift region. First, the DG forms dual conduction channels and shortens the forward current path, so reducing Ron,sp. The DG works as a vertical field plate to improve the breakdown voltage (BV) characteristics. Second, the BP forms a triple RESURF structure (T-RESURF), which not only increases the drift doping concentration but also modulates the electric field. This results in a reduced Ron,sp and an improved BV. Third, the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP. The BV of 325 V and Ron,sp of 8.6 m ??cm2 are obtained for the DG T-RESURF by simulation. Ron,sp of DG T-RESURF is decreased by 63.4% in comparison with a planar-gate single RESURF MOSFET (PG S-RESURF), and the BV is increased by 9.8%.