Fang Tang

A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors

Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC). This has traditionally made it difficult to implement large numbers of SAR ADC in parallel. This paper describes a compact 8b SAR ADC measuring only 348 μm×7 μm. It uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array; moreover, the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead. Any DAC error made during pDAC operation can be recovered later by an additional switching phase. Prototype measurements in 0.18 μm technology shows that the DACs figure-of-merit (FoM) is reduced from 61.3 fJ/step to 39.8 fJ/step by adopting pDAC switching with no apparent deterioration in Fixed-Pattern Noise (FPN) and thermal noise.

An 84 pW/Frame Per Pixel Current-Mode CMOS Image Sensor With Energy Harvesting Capability

In this paper, we present an ultra-low-power current-mode image sensor with energy harvesting capability. By biasing the in-pixel transconductance amplifier in triode region and using a pipelined 9-bit current-mode analog-to-digital converter (ADC), a power consumption as low as 84 pW/frame per pixel is achieved. Besides the ultra-low-power feature, the proposed 6T pixel can also be used as a solar cell by reconfiguring the in-pixel P+/Nwell photodiode, which can generate several micro watt power at Klux illumination levels. As a result, this energy harvesting imager is very suitable for wireless image sensor network applications. The test chip with a 128 × 96 pixel array resolution is fabricated using a 0.35 μ m CMOS technology. The random noise and the fixed pattern noise (FPN) in dark are 0.4% and 1%, respectively. In the energy harvesting mode, 4.85 μW power can be harvested using the reconfigurable pixel array.

A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADCs built-in capacitor array without any additional amplifier or memory. The ADC measures 490μm×7.4μm and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18 μm technology shows that the ADCs Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADCs mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.

Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme

This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μm CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.

An ultra-low power current-mode CMOS image sensor with energy harvesting capability

In this paper, an energy harvesting CMOS image sensor with ultra-low power consumption is presented. The proposed active pixel sensor (APS) operates in current-mode and a 9-bit flash series current-mode A/D converter unit together with its peripheral control circuitry are all integrated on chip. A power consumption as low as 84pW/frame per pixel is achieved by biasing the in-pixel transconductance amplifier in triode region and enabling the current-mode ADC only during the read-out phase. The imager can also be reconfigured into an energy harvesting mode, which can generate several micro watt power at K-lux illumination levels. The 128 } 96 array is fabricated in a 0.35µm technology. The total chip area is 8mm2 and the pixel pitch is 21µm with a 39% fill-factor. Experimental results of the fabricated chip illustrate its proper operation in both image capture and energy harvesting modes.

Low power dynamic logic circuit design using a pseudo dynamic buffer

In this paper, we propose a pseudo dynamic buffer (PDB) for footed domino logic circuit implementation. Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case. As a result, up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate. This PDB structure is applicable not only for Pull-down network (N-type) dynamic logic, but also for Pull-up networks (P-type). Simulation results illustrate improved performance using the proposed scheme compared to the conventional dynamic logic for different loading conditions, clock frequencies and logic functions. In addition, our proposed design reduces the clock loading from conventional three to two transistors. As a result, the proposed scheme significantly saves power due to lower load capacitance on the clock bus. Test structures are fabricated in 0.35@mm CMOS technology. Measurement results validate the proposed concept and illustrate power saving as compared to conventional design.

A 12 pJ/Pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image Sensor

Analog-to-information converters (AICs) take advantage of the limited information bandwidth in high-frequency signals to improve the energy efficiency of front-end data converters. High-resolution image sensors often convey limited information due to the spatial redundancy between neighboring pixels. This paper proposes a mixed-signal AIC which compresses each nonoverlapping 4 × 4 pixel block in a 816 × 640 pixel prototype active-pixel sensor (APS) imager. It combines an energy-efficient charge-pump bit-image processor (BIP) with an area-efficient successive-approximation-register-single-slope (SAR-SS) hybrid analog-to-digital converter (ADC) via a charge-transfer-amplifier (CTA). The AIC is fully dynamic and consumes no static power. The ADCs capacitor array doubles as a computational device for parts of the compression algorithm which reduces its sampling rate by a factor of four. The compressed data contains direct edge information and can be decoded by a very simple receiver. The fabricated prototype consumes 12 pJ per pixel at 111 fps in the image compression mode and 48 pJ per pixel at 28.7 fps in raw data mode (9 b per pixel) under the same clock rate. To the best of our knowledge, this is the most energy-efficient compressive CMOS image sensor ever reported in the literature, thanks to the proposed AIC.

Deep Learning With Grouped Features for Spatial Spectral Classification of Hyperspectral Images

This letter presents a novel deep learning algorithm for feature extraction from the hyperspectral images. The proposed method takes advantage of the knowledge that the features of the spatial-spectral data naturally fall into an array of groups with respect to different spectral bands. Aiming to reduce the influence of redundant spectral bands adaptively using unlabeled hyperspectral data, we incorporate the group information in the training algorithm of the deep neural network via a regularized weight-decay process. Experiments over different benchmarks of hyperspectral images show that the proposed method provides competitive solution with the state-of-the-art approaches.

80dB dynamic range 100KHz bandwidth inverter-based ΣΔ ADC for CMOS image sensor

A sigma delta (ΣΔ) ADC for sensing application is presented in this paper. Several techniques are adopted to implement a low power high dynamic range ADC. Firstly, a single-stage inverter replaces the commonly used differential amplifier, in order to reduce the static current. Secondly, the normal NMOS transistor in the inverter stage is replaced by a high threshold device. As a result, with the same transistor size and supply voltage, the gain of the inverter can be enhanced while the short circuit current can be reduced. Thirdly, the charge leakage due to the forward-based parasitic diode is eliminated by using a charge protection switch and rearranged reference scheme. The proposed ΣΔ ADC is implemented and fabricated using TSMC 0.18μm technology. The simulation result shows that for a 1.8V supply, 25MHz sampling frequency and 125 oversampling ratio, the power consumption is 63.7μW and 116μW, dynamic range is 80dB and 83dB, the ENOB is 11.5 and 11.7bit for a single-ended and a pseudo-differential configurations, respectively. The presented ADC scheme can be applied in a Full HD image sensor running at up to 50 frames/s.

A low power oscillator based temperature sensor for RFID applications

In this paper we present a temperature sensor based on a ring oscillator. The ring oscillator uses the CMOS thyristor delay element and has an extremely low power consumption of about 47nW at room temperature with a supply of 0.5V. Low power operation is achieved by eliminating the use of power hungry analog to digital converters (ADCs) at the sensor output. As shown the frequency increases linearly with temperature. The error in temperature sensing is around -1.8°C / +1°C with a resolution of 0.3°C. Simulation is carried out with Chartered Semiconductors 0.18μm technology. Owing to the extremely low power consumption, integration with a radio-frequency identification (RFID) tag is also possible.