Shengdong Hu

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsivT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/mum at tS = 0.1 mum. Expressions for EI and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an EI value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.

Realization of High Voltage (

A novel silicon-on-insulator (SOI) high-voltage device with a compound buried layer (CBL SOI) consisting of two oxide layers and a polysilicon layer between them is proposed. Its breakdown characteristic is investigated theoretically and experimentally. Theoretically, its vertical breakdown voltage (BV) is shared by two oxide layers; furthermore, the electric field in the lower buried oxide layer of EI2 is increased from about 78 to 454 V/mum by holes collected on the bottom interface of the polysilicon. Both result in an enhanced BV. Experimentally, 762-V SOI diode is obtained. The maximal temperature of CBL SOI diode is reduced by 16.9 K because a window in the upper buried oxide layer alleviates the self-heating effect.

≫ \hbox{700}

Abstract A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n + -regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n + -regions effectively enhance the electric field of the buried oxide layer ( E I ) and reduce the electric field of the silicon layer ( E S ), resulting in a high breakdown voltage ( V B ). It is shown by the simulations that the enhanced field Δ E I and reduced field Δ E S by the accumulated holes reach to 449xa0V/μm and 24xa0V/μm, respectively, which makes V B of ICI PSOI increase to 663xa0V from 266xa0V of the conventional PSOI on 5xa0μm silicon layer and 1xa0μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1xa0mW/μm.

V) in New SOI Devices With a Compound Buried Layer

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias V bg, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). V bg only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 V/mum of the conventional SOI to 457 V/mum at V bg = 0 V, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel low-reverse recovery charge superjunction MOSFET (SJ-MOSFET) with a p-type Schottky body diode is proposed in this letter. The device has a p-type Schottky contact on the p-pillar at the drain side. Electrons are prevented from injecting into the drain side by the p-type Schottky contact, and the total carrier concentration is greatly reduced. Compared with the conventional device, the proposed SJ-MOSFET has a lower reverse recovery charge and a larger soft factor. Simulated results show that the reverse recovery charge is reduced by 81.3% and 76.0% at 300 K and 400 K, respectively, with a metal work function of 4.5 eV. The optimized metal work function range is 4.3–4.6 eV.

Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

ABSTRACT An ultra-low specific on-resistance (Ron,sp) trench silicon-on-insulator (SOI) LDMOS is proposed in this paper. In this novel structure, a floating lateral metal field plate (FLFP) is introduced into the oxide trench of the conventional SOI LDMOS (con-TLDMOS) and connected to the gate outside the device working region. The oxide trench causes multidirectional depletion, which leads to electric field reshaping. The FLFP causes an assistant depletion effect especially for the trench surface regions, which significantly increases the doping concentration of the drift region (Nd). Therefore, a novel structure (FLFP-TLDMOS) with a breakdown voltage (BV) of 188 V and an Ron,sp of 1.05 mΩ·cm2 is obtained on a 4.8-μm-long drift region. Compared with the con-TLDMOS, the Ron,sp of the FLFP-TLDMOS can be reduced by about 54.3%; furthermore, its BV is maintained the same class with the con-TLDMOS, and the figure of merit is increased by 118%. Furthermore, the dynamic performance and self-heating effect of the novel structure are slightly improved compared with the conventional trench structure.

Low-Reverse Recovery Charge Superjunction MOSFET With a p-Type Schottky Body Diode

In order to achieve a high breakdown voltage (BV) for the SOI (Silicon-On-Insulator) power device in high voltage ICs, a novel high voltage n-channel lateral double-diffused MOS (LDMOS) with a lateral variable interface doping profile (LVID) placed at the interface between the SOI layer and the buried-oxide (BOX) layer (LVID SOI) is researched. Its breakdown mechanism is investigated theoretically, and its structure parameters are optimized and analyzed by 2D simulation software MEDICI. In the high voltage blocking state, the high concentration ionized donors in the depleted LVID make the surface electric field of SOI layer () more uniform and enhance the electric field of BOX layer (), which can prevent the lateral premature breakdown and result in a higher BV. Compared with the conventional uniformly doped (UD) SOI LDMOS, of the optimized LVID SOI LDMOS is enhanced by 79% from 119u2009V/μm to 213u2009V/μm, and BV is increased by 33.4% from 169u2009V to 227u2009V. Simulations indicate that the method of LVID profile can significantly improve breakdown voltage for the SOI LDMOS.