Farah B. Yahya

A 6.45

This paper presents a batteryless system-on-chip (SoC) that operates off energy harvested from indoor solar cells and/or thermoelectric generators (TEGs) on the body. Fabricated in a commercial 0.13 μW process, this SoC sensing platform consists of an integrated energy harvesting and power management unit (EH-PMU) with maximum power point tracking, multiple sensing modalities, programmable core and a low power microcontroller with several hardware accelerators to enable energy-efficient digital signal processing, ultra-low-power (ULP) asymmetric radios for wireless transmission, and a 100 nW wake-up radio. The EH-PMU achieves a peak end-to-end efficiency of 75% delivering power to a 100 μA load. In an example motion detection application, the SoC reads data from an accelerometer through SPI, processes it, and sends it over the radio. The SPI and digital processing consume only 2.27 μW, while the integrated radio consumes 4.18 μW when transmitting at 187.5 kbps for a total of 6.45 μW.

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This paper compares six different 8T SRAM bitcells targeting different design space requirements - such as reliability and low power/energy - for Internet of Things (IoT) applications. Different bitcells leverage the varying characteristics of high-threshold (high-VT) and standard-threshold (standard-VT) devices to affect SRAM metrics like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and variability. The reliability for each bitcell over process (intra- and inter-die variation) and temperature variation is also evaluated. Measured results for a commercial 130nm test chip compare the most promising two 8T bitcell structures targeting low leakage and low energy.

Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems

This paper evaluates the impact of different peripheral write assist techniques on the reliability and energy efficiency of Static Random Access Memory (SRAMs) in Body Sensor Networks (BSNs). The results of this characterization show that the best choice for a supply voltage and write assist combination varies based on the system level constraints and objectives. Further, factors outside the accessed cells such as half select stability dictate the optimal assist choice, the extent to which the assist should be applied, and the total array energy. Using data from a thorough study of assist options across VDDs, we establish strategies for supply voltage and assist selection based on system constraints to reduce the array energy. While VDD lowering assist technique provides the lowest array energy per operation of 8.5pJ at 0.5V when write delay is not constrained, negative bit line (NegBL) improves the write speed by 121X at the same voltage with 23pJ of energy.

Optimizing SRAM bitcell reliability and energy for IoT applications

This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub threshold voltages. We find that combining negative bitline (BL) for write assist with array VDD boosting for read assist is most effective for reducing the array VMIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM VMIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This paper also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in VMIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve VMIN for both the FinFET and the 130nm bit-cells.

Improving Reliability and Energy Requirements of Memory in Body Sensor Networks

This paper investigates the use of extremely low threshold voltage (VTh) for the select transistor in STT-RAM cell. While doing so intuitively improves its write margin, the extra current can also result in an MTJ oxide breakdown in the selected cell, as well as higher leakage current in an unselected cell inducing a false write in it. We thus propose an all-digital write driver to bias the selected source and bit lines (SL/BL) properly in order to guarantee a successful write operation while avoiding the above drawbacks. The proposed driver can be programmed per die to track die-to-die variations for maximum dynamic and leakage write energy reduction. The paper also describes the methodology used to design the cell and driver. Simulations in a 32nm commercial process show that a low-VTh NMOS select device provides 18X improvement in STT-RAM write-margin as compared to a conventional cell, while the proposed driver offers up to 37% reduction in write energy per bit as compared to a conventional write diver.

Combined SRAM read/write assist techniques for near/sub-threshold voltage operation

A 507nW self-powered SoC is demonstrated for ultra-low power (ULP) internet-of-things (IoT) applications. The SoC includes ULP system-in-package (SiP) interfaces that enable its harmonious integration with a radio transmitter (TX) and a non-volatile memory (NVM). The energy harvesting platform power manager (EH-PPM) powers the SoC as well as off-chip components and is optimized for low quiescent power. It supplies the SoC with 0.5V, 1.0V, and 1.8V and can also power ULP sensors and the SiP components while running an example shipping-integrity tracking algorithm. A power monitor (PM) cold-boots the SoC from NVM and adapts the systems power consumption. The tight integration between the SoCs blocks enables sub-μW operation.

Designing low-V Th STT-RAM for write energy reduction in scaled technologies

This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (VT) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power saving. A test chip implements a 1Kb 6T SRAM, an FIR filter, and a 51-stage RO to showcase how the technology works with circuit techniques to minimize energy. The 6T SRAM array operates reliably down to 200mV with a reduced leakage power of 7nW (85% lower compared to non-DDC devices). The FIR filter consumes just 4.5pJ/cycle operating at 0.36V at 200 KHz.

A battery-less 507nW SoC with integrated platform power manager and SiP interfaces

This paper presents an overview of various challenges, optimization strategies, and design requirements for subthreshold SRAM arrays targeting Ultra-Low Power (ULP) applications in the Internet of Things (IoTs). We study the impact of threshold voltage (VT) change due to process and temperature variations on various SRAM design decisions for ULP operation. We explore different solutions to enable reliable subthreshold operation ranging from technology to cell to architecture and assist. We also highlight the impact of process variations on optimal peripheral assist selection, and degree of assist requirements. We present trade-offs between reliability, energy, and performance to an application-specific SRAM design. Six different types of SRAM bitcells are compared for various subthreshold metrics to provide an optimal bitcell selection for the targeted application.

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic

This paper presents a lossless sensor data compression accelerator for power reduction in wireless body sensors. First, a low complexity compression algorithm is demonstrated for the first time on electrocardiogram (ECG) and acceleration sensor data. Second, the algorithm is implemented as a custom hardware accelerator on a health monitoring driven System on Chip (SoC) in a 130 nm process. The accelerator is closely integrated with the transmitter interface to minimize its contribution to system power and reduce user overhead. The accelerator adds only 4.4 nW processing overhead and reduces the required transmitter duty cycle by 3.7x, reducing the system power by 2.9x, and allowing the entire system to consume just 2.62 μW when transmitting ECG data at a 360 Hz sampling rate.

Subthreshold SRAM: Challenges, design decisions, and solutions

Reducing power consumption is a major concern in mobile applications, since they are battery operated and require high performance. In this paper, a novel technique to reduce the power consumed by embedded SRAM memory is introduced. The proposed method is an on-chip circuit to measure the optimal data retention voltage (DRV) of the SRAM array. The implemented DRV computing circuit consists of a built-in-self-test (BIST) unit, a DC-DC converter and some control logic. The proposed technique can be used to accurately measure the DRV to ensure the SRAM operates at its minimum energy point. The circuit was developed in 90nm technology and simulated using HSPICE. Monte-Carlo simulation of 100k samples determined the DRV as 150mV whereas the proposed technique showed that the DRV of the SRAM under test could be lowered to 80mV which would result in significant power savings.