Harsh N. Patel

Optimizing SRAM bitcell reliability and energy for IoT applications

This paper compares six different 8T SRAM bitcells targeting different design space requirements - such as reliability and low power/energy - for Internet of Things (IoT) applications. Different bitcells leverage the varying characteristics of high-threshold (high-VT) and standard-threshold (standard-VT) devices to affect SRAM metrics like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and variability. The reliability for each bitcell over process (intra- and inter-die variation) and temperature variation is also evaluated. Measured results for a commercial 130nm test chip compare the most promising two 8T bitcell structures targeting low leakage and low energy.

Improving Reliability and Energy Requirements of Memory in Body Sensor Networks

This paper evaluates the impact of different peripheral write assist techniques on the reliability and energy efficiency of Static Random Access Memory (SRAMs) in Body Sensor Networks (BSNs). The results of this characterization show that the best choice for a supply voltage and write assist combination varies based on the system level constraints and objectives. Further, factors outside the accessed cells such as half select stability dictate the optimal assist choice, the extent to which the assist should be applied, and the total array energy. Using data from a thorough study of assist options across VDDs, we establish strategies for supply voltage and assist selection based on system constraints to reduce the array energy. While VDD lowering assist technique provides the lowest array energy per operation of 8.5pJ at 0.5V when write delay is not constrained, negative bit line (NegBL) improves the write speed by 121X at the same voltage with 23pJ of energy.

Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications

In this paper, we explore an approximate logic synthesis approach to re-design adders for error-resilient applications. The objective is that the re-designed approximate adder reduces delay, power and area metrics, and thus, improves both functional and parametric yields due to decrease in the silicon area and delay, respectively. To ameliorate the Error Distance (ED)1 and Error Rate (ER)2 of the proposed approximate adder, we avail of the probability of carry-lifetimes and Error Detection and Correction (EDC) logic, respectively. We design the successive versions of the proposed approximate adder using PTM 32nm CMOS technology and simulate the net-lists in HSPICE environment. Simulation results show that for a 16-bit Ripple Carry Adder (RCA) with k = 6, 8 and 10 (k is the number of MSBs that are performed accurately), the proposed approach improves chip yield by 79.08%, 65.81% and 43.72%, and 89.63%, 74.44% and 52.63% with and without EDC logic, respectively.

Combined SRAM read/write assist techniques for near/sub-threshold voltage operation

This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub threshold voltages. We find that combining negative bitline (BL) for write assist with array VDD boosting for read assist is most effective for reducing the array VMIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM VMIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This paper also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in VMIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve VMIN for both the FinFET and the 130nm bit-cells.

A battery-less 507nW SoC with integrated platform power manager and SiP interfaces

A 507nW self-powered SoC is demonstrated for ultra-low power (ULP) internet-of-things (IoT) applications. The SoC includes ULP system-in-package (SiP) interfaces that enable its harmonious integration with a radio transmitter (TX) and a non-volatile memory (NVM). The energy harvesting platform power manager (EH-PPM) powers the SoC as well as off-chip components and is optimized for low quiescent power. It supplies the SoC with 0.5V, 1.0V, and 1.8V and can also power ULP sensors and the SiP components while running an example shipping-integrity tracking algorithm. A power monitor (PM) cold-boots the SoC from NVM and adapts the systems power consumption. The tight integration between the SoCs blocks enables sub-μW operation.

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic

This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (VT) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power saving. A test chip implements a 1Kb 6T SRAM, an FIR filter, and a 51-stage RO to showcase how the technology works with circuit techniques to minimize energy. The 6T SRAM array operates reliably down to 200mV with a reduced leakage power of 7nW (85% lower compared to non-DDC devices). The FIR filter consumes just 4.5pJ/cycle operating at 0.36V at 200 KHz.

Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications

Aggressive technology and supply voltage scaling has led to increasing concern for reliability. Optimizing power and energy with sub-threshold (sub-VT) operation exponentially increases the occurrences of both static and dynamic failures. With smaller node capacitances with each technology and supply scaling node, radiation-induced Single Event Upset (SEU) has become a critical design metric for Ultra-Low-Power (ULP) applications. In this paper, we explore the impact of radiation-induced soft errors on sub-threshold SRAM implemented in a Body Sensory Node (BSN) as an ULP application. We also demonstrate an exponential reduction in the critical charge (Qcrit) of a storage node with supply in near- and sub-VT design, resulting in a significant design consideration for the low-power applications. The huge process variation in sub-VT results in 3X Qcrit variation. Finally, we compare the trend of technology scaling and supply voltage scaling on Qcrit.

Subthreshold SRAM: Challenges, design decisions, and solutions

This paper presents an overview of various challenges, optimization strategies, and design requirements for subthreshold SRAM arrays targeting Ultra-Low Power (ULP) applications in the Internet of Things (IoTs). We study the impact of threshold voltage (VT) change due to process and temperature variations on various SRAM design decisions for ULP operation. We explore different solutions to enable reliable subthreshold operation ranging from technology to cell to architecture and assist. We also highlight the impact of process variations on optimal peripheral assist selection, and degree of assist requirements. We present trade-offs between reliability, energy, and performance to an application-specific SRAM design. Six different types of SRAM bitcells are compared for various subthreshold metrics to provide an optimal bitcell selection for the targeted application.

A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and V MIN tracking canary sensors

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based VMIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V.