Fathi A. Farag

Input-output Rail-to-Rail CMOS CCII for low voltage-low power applications

This paper presents a novel circuit design for input-output Rail-to-Rail CMOS Second Generation Current Conveyor (CCII) for low voltage and low power applications. The designed circuit is structured from a single stage Rail-to-Rail Operational Amplifier (Op-Amp) and a conventional CMOS inverter as a class AB amplifier. Therefore, it provides a high wide range for input signal and high output current driving capability operation. In this paper, a new technique for an automated design script is created to produce a constant trans-conductance (gm) for the Rail-to-Rail Op-Amp using Open Command Environment (OCEAN) script language. The proposed Rail-to-Rail Op-Amp is based on a DC level shifter technique, which is cited at the input stage. This script allows the design problem to be cast as a program. Therefore, it offers an efficient, reliable, and fast way to implement high-performance of analog integrated circuits. Moreover, the physics-based gm/ID characteristic is used that is more suitable for short channel transistors in sub-micron processes. The circuit is simulated in IBM 0.13? CMOS technology with a single power supply 1.5-V. Virtuoso layout editor tool with caliber tools from Mentor Graphics are used to carry out the layout of the proposed circuit. The chip is fabricated by MOSIS Educational Program (MEP) and is tested to evaluate the performance of the proposed circuits. The measured and simulation results indicate a good agreement. A novel circuit design for input-output Rail-to-Rail CMOS CCII for low voltage and low power applications is proposed.A new technique for an automated design script is created using Open Command Environment script language.The physics-based gm/ID characteristic is used that is more suitable for short channel transistors in sub-micron processes.Virtuoso layout editor tool with caliber tools from Mentor Graphics are used to carry out the layout.The chip is fabricated by MOSIS Educational Program.

New active capacitance multiplier for low cutoff frequency filter design

This paper presents a new topology for an active capacitance multiplier. This circuit affords a technique to implement a high capacitance value using a small on-chip capacitor. The proposed capacitance multiplier is build up by cascading current multiplier cells (CMC). The circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps only. The capacitance multiplier is employed in the design of a second-order LPF with a programmable cutoff frequency. The cutoff frequency can be as low as 65 Hz using an on-chip capacitor of 1pF only. The static power dissipation is equal to 3 mW. Some practical considerations are discussed. The circuit is simulated using CMOS 0.13 mum process. Simulation results show good agreement with the analytical calculations.

Efficient enhancement and matching for iris recognition using SURF

Iris recognition is gaining more attention and the development of the field is increasing rapidly. This paper presents a complete iris recognition system. The iris features are obtained using Speeded Up Robust Features (SURF) after enhancing the image using Contrast Limited Adaptive Histogram Equalization (CLAHE). A novel matching algorithm based on applying fusion rules at different levels is proposed. The algorithm has the advantage of reduced data storage and fast matching. It can also handle efficiently the problem of rotation, scaling, illumination variation and occlusions. The proposed algorithm is implemented and tested using CASIA (V4) database. The recognition accuracies obtained are 99% using left images and 99.5% using right images. Results show that fusion of right and left images scores increases the recognition accuracy. The recognition accuracies obtained after fusion are 99.5% and 100% using minimum and sum rules respectively. Moreover, the proposed algorithm has an excellent robustness with respect to increasing the number of subjects.

Segmentation of breast cancer lesion in digitized mammogram images

Segmentation or abnormality detection is an essential step in mammographic computer-aided diagnosis (CAD) systems. This paper presents a novel computerized method to automatically detect mass lesions (i.e. detect suspicious locations containing abnormalities inside the breast area) on digitized mammogram images. In particular, we implement an enhanced version of the region growing algorithm for segmentation of mass lesions that can be implemented in a complete CAD system. The proposed algorithm uses region growing technique with a novel automatic threshold estimation method to detect and segment mass lesions. The proposed algorithm detects masses by analyzing a single view of the breast (i. e. Medio-Lateral oblique (MLO) view or Cranio-Caudal (CC) view). The performance of the proposed algorithm was evaluated using two mammogram databases from two different hospitals. The matching percentage of the segmented regions obtained by the proposed algorithm is 83% with respect to the ground truth (i.e. reference determined by an expert radiologist). The proposed algorithm showed promising performance when compared with other commonly used segmentation techniques.

Band-limited histogram equalization for mammograms contrast enhancement

Early detection of breast cancer is the most effective method of reducing mortality. Mammography is at present the best available technique for early detection of breast cancer. The most common breast abnormalities that may indicate breast cancer are masses and calcifications. In mammograms, cancer is not easily detected by the eyes because of the bad imaging quality. To improve the correct diagnosis rate of cancer, image-enhancement techniques are often used to enhance the image and aid the radiologists. In this paper, we introduce a new algorithm for mammograms contrast enhancement. The proposed algorithm performs band-limited histogram equalization (BLHE) for certain intensity band of the mammogram histogram. According to the opinion of radiologist, the proposed algorithm showed promising performance when applied on several mammography images. In addition, the proposed algorithm was combined with a wavelet-based contrast enhancement method to further improve its performance.

Digitally programmable CMOS current-conveyor circuit for filter design

This paper presents a new topology for a fully digitally programmable current-mode filter. The proposed scheme is based on the current conveyor cell in [1]. The circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps only. The proposed circuit is employed to implement digitally variable capacitor for low cut off frequency filter design. The proposed circuits have been designed and simulated using the IBM CMOS 0.13 µm process. Error analysis is also provided in detail and performance improvement is discussed. Simulation results show good agreement with the analytical calculations. The static power dissipation is equal to 0.1mW from 1.5V supply.

Fully integrated active filter design forultra low frequency application

This paper presents a new active capacitance multiplier circuit, by which it is possible to obtain higher capacitance values. The capacitance multiplier is based on cascaded current multiplier cells (CMC). The proposed circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps. The capacitance multiplier is employed in the design of a first order LPF with a cutoff frequency as low as 135 Hz using an on-chip capacitor of 1 pF only. The circuit is simulated in CMOS 0.13 mum process. Simulation results show close agreement with the analytical calculations.

CMOS buffer amplifier for wide bandwidth applications

This paper describes a new configuration of a CMOS buffer circuit. The new buffer is based on a Flipped Voltage Follower (FVF) with feedback in order to enhance the transconductance of the buffer as well as linearity. The proposed cell can be used as a very high bandwidth buffer to drive high capacitive loads. The employed feedback enhances the overall transconductance while minimizing the loading effect. The circuit is designed and simulated by using 0.13 mum CMOS process. The proposed buffer is compared with a conventional voltage-follower and flipped-voltage-follower for a capacitive load up to 30 pF. Simulation results show a bandwidth of 145 MHz for a capacitive load of 30 pF. The power consumption is 2.4 mw for 1.5 V power supply.

Digitally-Controlled Variable-Gain-Amplifier based on current conveyor with opamp and inverters only

This paper presents a new topology of a Digitally-Controlled current-mode-Variable-Gain-Amplifier “DCVGA”. A fully differential DCVGA is proposed, which improves the VGA performance. The proposed circuit is based on the current conveyor cell reported in [1]. The circuit is suitable for low-power low-voltage applications since it is based on CMOS inverters. The proposed DCVGA achieves linear-in-dB gain variation at 1dB resolution. The variable gain is tuned from −5 to 36 dB. The proposed circuits have been designed and simulated using 0.13 µm IBM CMOS process. The simulation results show good performance in both gain-tuning ability and frequency response. Also, the 3-dB bandwidth is about 50 kHz at maximum gain. The power dissipation is 2.1mW from 1.5V supply voltage.

D8. Low power pseudo CMOS memory cell for matrix ROM applications

In this paper, a low power pseudo CMOS inverter for matrix ROM realization is presented. The proposed circuit consists of grounded gate pulled up pMOST and a conventional CMOS inverter in cascaded. Thus, the proposed cell is suitable for low power circuit referred to the conventional pseudo inverter. The free hand designed equations are driven based on square law MOSFET model. The presented inverter is used for representing the memorized data 1 or 0, which is the ROM memory basic element. The designed cell features great saving of power consumption at least 33%, and provides high performance. The proposed pseudo-CMOS inverter consumed power less than 20μW/cell using 1.5-supply voltage, and it is designed and simulated using the IBM 130nm CMOS technology.