Fawnizu Azmadi Hussin

An Energy Efficient Cross-layer Network Operation Model for IEEE 802.15.4-based Mobile Wireless Sensor Networks

IEEE 802.15.4 mobile wireless sensor networks (MWSNs) have been investigated in literature. One major finding is that these networks suffer from control packet overhead and delivery ratio degradation. This increases the networks energy consumption. This paper introduces a cross-layer operation model that can improve the energy consumption and system throughput of IEEE 802.15.4 MWSNs. The proposed model integrates four layers in the network operation: 1) application (node location); 2) network (routing); 3) medium access control (MAC); and 4) physical layers. The location of the mobile nodes is embedded in the routing operation after the route discovery process. The location information is then utilized by the MAC layer transmission power control to adjust the transmission range of the node. This is used to minimize the power utilized by the network interface to reduce the energy consumption of the node(s). The model employs a mechanism to minimize the neighbor discovery broadcasts to the active routes only. Reducing control packet broadcasts between the nodes reduces the networks consumed energy. It also decreases the occupation period of the wireless channel. The model operation leads the network to consume less energy while maintaining the network packet delivery ratio. To the best of our knowledge, the presented operational model with its simplicity has never been introduced. Through simulation-based evaluations, the proposed model outperforms the conventional operation of IEEE 802.15.4-based network and the energy efficient and QoS aware multipath routing protocol in terms of energy consumption by roughly 10%, twice less control packet overhead, on-par end-to-end delays and comparative packet delivery ratios.

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

In this paper, two wrapper designs are proposed for core- based test application based on Networks-on-Chip (NoC) reuse. It will be shown that the previously proposed NoC wrapper does not efficiently utilize the NoC bandwidth, which may result in poor test schedules. Our wrappers (Type 1 and Type 2) complement each other to overcome this inefficiency while minimizing the overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while the Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel bandwidth and test time constraints, resulting in very little or no increase in the test application time compared to conventional TAM approaches.

Road sign detection and recognition system for real-time embedded applications

In this paper, we propose a road sign detection and recognition algorithm for an embedded application, which requires computationally simple but accurate algorithms. The algorithm is developed by using the Hue Saturation Intensity (HSI) color space to segment the road signs color (red, yellow, blue and white) and the regions of interest (ROI) in order to locate and determine the shape of the road sign (diamond, square, hexagonal and circular) in real street-view images. The shape is then used to classify road signs into four categories, i.e. warning, mandatory, prohibitory and informational signs. The characteristics of the shapes such as area and perimeter variables are used to identify the symbols in the road signs. These variables are compared with the template library which we have developed. The proposed algorithm is tested on the Malaysias road signs which are captured on the roadside in their real environment. Experimental results on the accuracy of the road sign detection are reported in this paper. The proposed algorithm will be implemented in a real time embedded system using Xilinx Video Starter Kit Board- Spartan-3a DSP 3400A Edition.

Optimization of Processor Architecture for Image Edge Detection Filter

In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications.

Power-Constrained SOC Test Schedules through Utilization of Functional Buses

In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the generation of a complete test schedule that efficiently utilizes the functional bus under a power constraint is described. The test schedule is composed of a set of test vector delivery sequences in small chunks, denoted as packets. The utilization of small packet sizes optimizes the functional bus utilization. The experimental results show that the methodology is highly effective compared to previous approaches that do not use the functional bus. The strong results of the proposed approach are particularly highlighted when small bus widths are considered, an important consideration in current SOC designs where increasingly larger bus widths pose routing and reliability challenges.

SEOS: Hardware Implementation of Real-Time Operating System for Adaptability

Real-Time Operating System (RTOS) is widely used in real time embedded system for computing resource management. It is commonly implemented as fundamental layer in software framework. However, RTOS inevitably causes extra overhead and latency to the system. One of the innovative approaches to improve the overhead and latency is to bring the RTOS out from software framework and implement as hardware component. For past decades, researches had proved that significant performance improvement can be achieved by implementing RTOS in hardware. However, these research outcomes failed to get wide acceptance in commercial products. We postulate that the lacking of interest in commercial community on hardware approached RTOS is due its high level of difficulty in adaptation process. Adapting hardware based RTOS in embedded system requires in depth knowledge on operating system as well as significant amount of manpower resources. This makes the hardware RTOS unpopular despite of the performance offered. This paper proposed a Simple and Effective hardware based Real-Time Operating System (SEOS) designed to provide high adaptability for ease of hardware RTOS adaptation, at the same time significantly improved the performance. Experimental result shows that SEOS has great performance advantages over software based RTOS.

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

An integrated test scheduling methodology for multiprocessor system-on-chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology.

On testing of MEDA based digital microfluidics biochips

Recent years have seen rapid progress in using digital microfluidics based biochips for biomedical assays. The testing and reliability of these biochips is crucial when they are used in point-of-care diagnostics applications. As the scalability and complexity of biomedical assays increases, there is a need for efficient testing methodologies to ensure reliability of these biochips. The conventional testing methodologies will not be sufficient for the recently proposed and highly scalable Micro-electrode-dot array (MEDA) architecture based digital microfluidics. This is because of the advanced fluidic movement operations incorporated in the MEDA architecture. This paper investigates the testing methodologies for conventional digital microfluidics based biochips and their relevancy to the MEDA architecture based digital microfluidics biochips.

Shape-based road sign detection and recognition for embedded application using MATLAB

In this paper, we propose a road sign detection and recognition algorithm for an embedded application. The algorithm is based on the Hough transform method to detect lines in order to identify and determine the shape of the road sign. Shape measurements are currently employed to identify the road sign ratios of area and perimeter. The variables are compared with the template library which we have developed. In order to evaluate the accuracy, the proposed algorithm was tested on most of the Malaysian road signs, and the results are reported in this paper. Successful detection and recognition rate is about 83.67%.

Serpent encryption algorithm implementation on Compute Unified Device Architecture (CUDA)

CUDA is a platform developed by Nvidia for general purpose computing on Graphic Processing Unit to utilize the parallelism capabilities. Serpent encryption is considered to have high security margin as its advantage; however it lacks in speed as its disadvantage. We present a methodology for the transformation of CPU-based implementation of Serpent encryption algorithm (in C language) on CUDA to take advantage of CUDAs parallel processing capability. The proposed methodology could be used to quickly port a CPU-based algorithm for a quick gain in performance. Further tweaking, as described in this paper through the use of a profiler, would further increase the performance gain. Result based on the integration of multiple block encryption in parallel shows throughput performance of up to 100 MB/s or more than 7X performance gain.