Noohul Basheer Zain Ali

Optimization of Processor Architecture for Image Edge Detection Filter

In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications.

SEOS: Hardware Implementation of Real-Time Operating System for Adaptability

Real-Time Operating System (RTOS) is widely used in real time embedded system for computing resource management. It is commonly implemented as fundamental layer in software framework. However, RTOS inevitably causes extra overhead and latency to the system. One of the innovative approaches to improve the overhead and latency is to bring the RTOS out from software framework and implement as hardware component. For past decades, researches had proved that significant performance improvement can be achieved by implementing RTOS in hardware. However, these research outcomes failed to get wide acceptance in commercial products. We postulate that the lacking of interest in commercial community on hardware approached RTOS is due its high level of difficulty in adaptation process. Adapting hardware based RTOS in embedded system requires in depth knowledge on operating system as well as significant amount of manpower resources. This makes the hardware RTOS unpopular despite of the performance offered. This paper proposed a Simple and Effective hardware based Real-Time Operating System (SEOS) designed to provide high adaptability for ease of hardware RTOS adaptation, at the same time significantly improved the performance. Experimental result shows that SEOS has great performance advantages over software based RTOS.

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market.

On testing of MEDA based digital microfluidics biochips

Recent years have seen rapid progress in using digital microfluidics based biochips for biomedical assays. The testing and reliability of these biochips is crucial when they are used in point-of-care diagnostics applications. As the scalability and complexity of biomedical assays increases, there is a need for efficient testing methodologies to ensure reliability of these biochips. The conventional testing methodologies will not be sufficient for the recently proposed and highly scalable Micro-electrode-dot array (MEDA) architecture based digital microfluidics. This is because of the advanced fluidic movement operations incorporated in the MEDA architecture. This paper investigates the testing methodologies for conventional digital microfluidics based biochips and their relevancy to the MEDA architecture based digital microfluidics biochips.

Serpent encryption algorithm implementation on Compute Unified Device Architecture (CUDA)

CUDA is a platform developed by Nvidia for general purpose computing on Graphic Processing Unit to utilize the parallelism capabilities. Serpent encryption is considered to have high security margin as its advantage; however it lacks in speed as its disadvantage. We present a methodology for the transformation of CPU-based implementation of Serpent encryption algorithm (in C language) on CUDA to take advantage of CUDAs parallel processing capability. The proposed methodology could be used to quickly port a CPU-based algorithm for a quick gain in performance. Further tweaking, as described in this paper through the use of a profiler, would further increase the performance gain. Result based on the integration of multiple block encryption in parallel shows throughput performance of up to 100 MB/s or more than 7X performance gain.

Space Vector PWM for PMSM simulation using Matlab Simulink

Space Vector PWM (SVPWM) model is often built based on high-level functions and verified based on the output of the inverter or the model of the electrical motor with best possible accuracy. However, SVPWM implementation on digital hardware such as Field Programmable Gate Array (FPGA) and Application-specific Integrated Circuit (ASIC) is constrained by the limited resources and computation accuracy in these digital hardware compared to the mathematical model. The paper proposed a method that utilizes Matlab Simulink and Fixed-Point Toolbox to construct hardware-amenable SVPWM model. Using the proposed model, it is possible to estimate the digital hardware resources used and analyze the accuracy of the system before the actual designing process takes place. The model has been simulated and verified with signal switching patterns and output signals from the model of the electrical motor. Based on functional comparisons, it was found that the outputs of the SVPWM model are almost identical to the digital hardware implementation.

Automatic generation of test instructions for structural faults in processor cores using satisfiability

Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework to generate the test program based on instructions set architecture (ISA) to test structural faults in processor cores. The proposed methodology framework made three major contributions. First, the use of effective conjunctive normal formula (CNF) encoding and instruction set architecture (ISA) prunes the combinational and sequential search space. Second, the modular based test generation and use of instruction set architecture (ISA) considerably reduces the test generation time. Third, an automatic generation of test instructions for structural faults.

Fault Modeling and Simulation of MEDA Based Digital Microfluidics Biochips

The research in the area of digital micro fluidics biochips testing is rapidly growing. The recently proposed Micro-electrode Dot Array (MEDA) based digital micro fluidics architecture allows dynamic grouping of the micro-electrodes to form the desired shape of droplets. As these kinds of system are used in safety critical applications, their reliability is crucial. The testing of MEDA architecture is a challenging problem due to the involvement of multiple micro-electrodes for various operations. This paper presents the fault models associated with the MEDA architecture for one as well as multiple micro-electrodes. An oscillation based testing model is proposed to measure the frequency of the droplet in fault free and faulty case in terms of capacitance variation, which is shown to be directly related to the droplet volume. Simulation results from oscillation based testing model for the case of droplet electrode short fault shows a significant increase in the oscillation frequency as the capacitance of droplet decreases.

An improved distributed scheduling algorithm for wireless sensor networks

The emergence of low power consumption, high data rate and small size sensor network applications, has increased the demand for high-performance network services. To meet this challenge, we propose an Improved Distributed Scheduling Algorithm (IDSA), a novel heuristic scheduling technique that can provide effective collision free broadcasting, lower energy consumption, minimum message overhead and enhanced channel utilization. In contrast to earlier traditional scheduling algorithms of medium access control (MAC), which are generally designed for sequential slot assignments, this paper presents an improved algorithm for distributed scheduling. The IDSA has several unique features. First, it optimizes energy through collision free transmission by scheduling conflict-free slots. Second, it can adapt the changes in topology explicitly without reconstructing the global transmission schedule with minimum message overhead. Furthermore, the IDSA also provides improved performance in terms of message overhead, slot assignment per round and energy consumption. Simulation results show that the IDSA significantly outperforms a representative distributed random slot assignment algorithm (DRAND).

Detectability analysis for resistive open faults with dynamic supply voltage scaling awareness

Dynamic supply voltage scaling (DVS) is an efficient and practical design technique to reduce power consumption in VLSI devices. Due to the multiple voltage operating environment and the supply voltage dependent behavior of physical faults, obtaining a minimal test set which gives the best fault coverage is challenging. Researchers have showed that testing of resistive opens is best achieved at high supply voltage. However based on our experimental results on ISCAS-85 circuits it is shown that is not always the case for DVS enabled designs. This paper analyzes and identifies different detectability patterns for resistive open faults in such designs. Additionally it discussed the multi-VDD testing and its necessity to achieve 100% fault coverage.