Fayong Liu
University of Southampton
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Fayong Liu.
Scientific Reports | 2018
Z. Li; Moïse Sotto; Fayong Liu; Muhammad Husain; Hiroyuki Yoshimoto; Yoshitaka Sasago; Digh Hisamoto; Isao Tomita; Yoshishige Tsuchiya; Shinichi Saito
The Random Telegraph Noise (RTN) in an advanced Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is considered to be triggered by just one electron or one hole, and its importance is recognised upon the aggressive scaling. However, the detailed nature of the charge trap remains to be investigated due to the difficulty to find out the exact device, which shows the RTN feature over statistical variations. Here, we show the RTN can be observed from virtually all devices at low temperatures, and provide a methodology to enable a systematic way to identify the bias conditions to observe the RTN. We found that the RTN was observed at the verge of the Coulomb blockade in the stability diagram of a parasitic Single-Hole-Transistor (SHT), and we have successfully identified the locations of the charge traps by measuring the bias dependence of the RTN.
Archive | 2018
Kouta Ibukuro; Fayong Liu; Muhammad Husain; Z. Li; Isao Tomita; Yoshishige Tsuchiya; H.N. Rutt; Shinichi Saito
Dataset supports: Liu, F. et al (2018). Manipulation of random telegraph signals in a silicon nanowire transistor with a triple gate. Nanotechnology. DOI:10.1088/1361-6528/aadfa6
Archive | 2018
Fayong Liu; Muhammad Husain; Z. Li; Sotto, Moise, Sala Henri; Daniel Burt; J. D. Fletcher; M. Kataoka; Yoshishige Tsuchiya; Shinichi Saito
Dataset supports: Liu, F. et al (2016). Transport properties in silicon nanowire transistors with atomically flat interfaces. 1-2. Paper presented at 2017 1st Electron Devices Technology and Manufacturing Conference (EDTM2017), Japan.
Nanotechnology | 2018
Fayong Liu; Kouta Ibukuro; Muhammad Husain; Z. Li; Joseph Hillier; Isao Tomita; Yoshishige Tsuchiya; H.N. Rutt; Shinichi Saito
Manipulation of carrier densities at the single electron level is inevitable in modern silicon based transistors to ensure reliable circuit operation with sufficiently low threshold-voltage variations. However, previous methods required statistical analysis to identify devices which exhibit random telegraph signals (RTSs), caused by trapping and de-trapping of a single electron. Here, we show that we can deliberately introduce an RTS in a silicon nanowire transistor, with its probability distribution perfectly controlled by a triple gate. A quantum dot (QD) was electrically defined in a silicon nanowire transistor with a triple gate, and an RTS was observed when two barrier gates were negatively biased to form potential barriers, while the entire nanowire channel was weakly inverted by the top gate. We could successfully derive the energy levels in the QD from the quantum mechanical probability distributions and the average lifetimes of RTSs. This study reveals that we can manipulate individual electrons electrically, even at room temperature, and paves the way to use a charged state for quantum technologies in the future.
ieee electron devices technology and manufacturing conference | 2017
Z. Li; Moïse Sotto; Fayong Liu; Muhammad Husain; I. Zeimpekis; Hiroyuki Yoshimoto; Kazuki Tani; Yoshitaka Sasago; Digh Hisamoto; J. D. Fletcher; M. Kataoka; Yoshishige Tsuchiya; Shinichi Saito
We have found a systematic way to identify the bias conditions to observe the Random-Telegraph-Noise (RTN) in advanced Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). We measured a p-type MOSFET at 2K, and found narrow bias conditions to observe the RTN presumably caused by charge trapping and de-trapping, which were only observed at low temperatures. It will pave the way to address the nature of a trap, which will be useful to understand the mechanism of RTN to secure the reliability.
ieee electron devices technology and manufacturing conference | 2017
Fayong Liu; Muhammad Husain; Z. Li; Moïse Sotto; Daniel Burt; J. D. Fletcher; M. Kataoka; Yoshishige Tsuchiya; Shinichi Saito
We have fabricated ultra-narrow (sub-10 nm) short channel (100 nm) silicon (Si) nanowire transistors with atomically flat interfaces based on Si-on-Insulator (SOI) substrates. The raised source and drain electrodes were patterned together with the gate electrode. The smaller threshold voltage in the narrower nanowire suggests self-limiting oxidation during the gate oxide formation.
ieee electron devices technology and manufacturing conference | 2017
Daniel Burt; Abdelrahman Al-Attili; Z. Li; Fayong Liu; Katsuya Oda; Naoki Higashitarumizu; Yasuhiko Ishikawa; Osvaldo M. Querin; F. Y. Gardes; R. W. Kelsall; Shinichi Saito
Bi-axially strained Germanium (Ge) is an ideal material for Silicon (Si) compatible light sources, offering exciting applications in optical interconnect technology. By employing a novel suspended architecture with an optimum design on the curvature, we applied a biaxial tensile strain as large as 0.85% to the central region of the membrane.
international conference on group iv photonics | 2018
James Byers; K. Debnath; Hideo Arimoto; Muhammad Husain; Moïse Sotto; Z. Li; Fayong Liu; Ali Z. Khokhar; K. Kiang; Stuart A. Boden; D. J. Thomson; Graham T. Reed; Shinichi Saito
Archive | 2018
Daniel Burt; Abdelrahman Al-Attili; Z. Li; Fayong Liu; Naoki Higashitarumizu; Yasuhiko Ishikawa; Ozz Querin; F. Y. Gardes; R. W. Kelsall; Shinichi Saito; Katsuya Oda
Journal of the Physical Society of Japan | 2018
Shinichi Saito; Z. Li; Hiroyuki Yoshimoto; Isao Tomita; Yoshishige Tsuchiya; Yoshitaka Sasago; Hideo Arimoto; Fayong Liu; Muhammad Husain; Digh Hisamoto; H.N. Rutt; Susumu Kurihara