Fayrouz Haddad

A reconfigurable inductor-less CMOS low noise amplifier for multi-standard applications

This paper presents a reconfigurable inductor-less CMOS low noise amplifier (LNA) for multi-standard wireless applications. The LNA is designed to address PCS1900, UMTS, WLANb/g and Bluetooth frequency bands. The LNA is based on two cascaded stages. The first stage is a resistive feedback amplifier which achieves a wideband matching in order to address the different application frequency bands while performing a low noise figure. The second stage is a cascode amplifier with an active output LC resonator in order to select the desired bandwidth while achieving high gain and low surface area. The proposed multi-standard LNA, implemented in a 0.13μm CMOS technology achieves more than 26dB gain from 1.8 to 2.4GHz for a noise figure less than 3.4dB. The input and output return losses S11 and S22 are lower than -12dB and -16dB respectively. The LNA consumes 9.6 mA from 1.2V supply voltage and occupies a chip area of 0.165mm2 including pads.

An Enhanced Design of Multi-band RF Band pass Filter Based on Tunable High-Q Active Inductor for Nano-satellite Applications

This paper describes the design of a novel cascode-grounded tunable active inductor and its application in an active band-pass filter (BPF) suitable for multi-band radio frequency (RF) front-end circuits. The proposed active inductor circuit uses feedback resistance to improve the equivalent inductance and the quality factor. The novelty of this work lies on the use of a few number of multi-finger transistors, which allows reducing strongly the power consumption and the silicon area. In other words, we demonstrate that the use of variable P-type Metal-Oxide-Semiconductor (PMOS) resistor and controllable current source have a good potential for wide tuning in terms of inductance value, quality factor and frequency operation. The RF BPF is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multi-band operation is achieved through control voltages. The designed active inductor and RF BPF have been implemented in a standard 0.13μm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results are compared between schematic and post-layout design for inductance value, quality factor, transmission coefficient S21 and noise. This design yields encouraging results: the inductance value can be tuned from 10.94 to 44.17nH with an optimal quality factor around 2,581. In addition, the center frequency of the BPF can be tuned between 2 and 4.84GHz with an average insertion loss of 10.92±0.31dB. Throughout this range, the noise figure is between 10.49 and 9.22dB with an input referred 1dB compression point of −0.25dBm and IIP3 of 7.36dBm. The filter occupies 25.43μm×21.56μm of active area without pads and consumes between 2.38 and 2.84mW from a 1V supplying voltage.

A very low phase noise fully integrated CMOS quadrature LC oscillator for 2.4 GHz bluetooth/WLAN applications

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. The QVCO could be tuned between 2.41 and 2.64 GHz, and showed a phase noise of -139 dBc/Hz at 1 MHz offset frequency from the carrier across the whole tuning range, for a current consumption of 20 mA with 2.5-V power supply. A figure-of-merit of -190 dBc/Hz is observed.

Radio frequency tunable polyphase filter design

Polyphase filters are widely used in radio frequency (RF) receivers either to generate accurate quadrature signals or to reject the image. Analytical modeling of passive polyphase filter suitable for RF front-end applications is exposed. This analytical study has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component matching and parasitics reduction techniques have been taken into account. Tunable RC polyphase filter, suitable for multi-standard applications, has been fabricated in 0.13-µm CMOS technology.

Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling

In modern electronic systems, PLLs are widely used for frequency synthesis applications. PLLs have a mixed analog-digital nature, which makes difficult to characterize its overall non-linear behavior using general theory of feedback system. To simulate the transient behavior of the PLL often the circuit level simulator is used. The frequency divider circuit separates the loop in low and high frequency parts leading to a small sampling time and a high simulation time, which are major technological bottlenecks using behavioral or transistor level models. In this paper, electrical simulations of an arbitrary ordered PLL operating with a voltage switched charge pump (VSCP) are performed. By simulating each block of the VSCP-PLL within the loop using transistor level model, the results were used to setup macroscopic parameters within the Event-Driven model. The Event-Driven simulation efficiently characterizes the off-locking transient domain in a very short time. The Event-Driven simulations are validated by transistor level simulations of arbitrary ordered integer-N VSCP-PLL designed in Cadence (Virtuoso) using CMOS technologies (130nm and 65nm).

Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach

The charge-pump phase locked loop (CP-PLL) is a mostly used integrated circuit (IC) in various modern electronics applications to perform several functions. Due to its mixed analog and digital nature, often circuit level simulators are used to characterize its overall nonlinear dynamic behavior. Since the existing analytical methods are not efficient to account non-ideal and non-linear effects. Furthermore, considering a CP-PLL for frequency synthesis function, a low and high frequency part result in very long simulation times. Consequently, Spice like electrical simulator do not provide a quick assessment of the overall non-linear dynamic behavior of the CP-PLL. Additionally the PVT (Process, Voltage, and Temperature) variations are the most important aspect of the design flow to achieve a robust system. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs (VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the macroscopic behavior and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulations with a good agreement in accuracy and speed-up factor of 60,000 &7,000 for 2nd and 3rd order PLL is achieved respectively.

Exact and approximated discrete-time non-linear models of voltage switched CP-PLL

The charge-pump phase locked loop (CP-PLL) is a mixed signal system and it is a challenging task for a designer to analyze the exact switching behavior of the PLL using any general concept of feedback systems. As the order of the loop filter (LF) is enhanced to cancel pre-filter noise and spurious signals, the more complexity in analysis is inevitable. The PLL operating with a voltage switched charge-pump (VSCP) is a complicated system, since the system representation is not unique in all switching states of the phase and frequency detector (PFD). Therefore, it is not possible to characterize the system with a unique transfer function. In this paper, an exact discrete-time non-linear model of the VSCP-PLL is presented using efficient Event Driven (ED) modeling. By assuming a constant voltage at control node in the zero-state, the approximation model is demonstrated, which can be sufficient to use without complicating the analysis up to some extent. The ED-simulation of the exact model is validated using an equivalent transistor level model designed in 130nm CMOS process. The ability of both exact and approximation model is mapped applying a ramping reference frequency.

Ultra low power and high gain switched CMOS g m - boosted current reused mixer for wireless multi-standard applications

An ultra low power and low voltage down conversion mixer is presented in this paper for the frequency band of 1.8-2.4GHz. Designed in 0.18 µ m CMOS technology, the double balanced proposed mixer is composed by two cascaded stages. The first one is based on cross coupled capacitors technique in current reused topology providing a high voltage gain, while the second one employs a current reused transducer coupled to LO driven inverters to perform the down conversion. All the devices operate on moderate inversion for better trade-off between gain, linearity, and low power consumption. The post layout simulation shows a 23dB of voltage gain conversion, an IIP3 of -2dBm, with 300 µ W of power consumption under 0.9V voltage supply.

A Very Low Phase Noise Fully Integrated Quadrature LC Oscillator for 2.4 GHz band Applications

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. The QVCO could be tuned between 2.41 and 2.64 GHz, and showed a phase noise of -139 dBc/Hz at 1 MHz offset frequency from the carrier across the whole tuning range, for a current consumption of 20 mA with 2.5-V power supply. A figure-of-merit of -190 dBc/Hz is observed.

A very low phase noise fully integrated quadrature LC oscillator for 2.4 GHz band applications

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. The QVCO could be tuned between 2.41 and 2.64 GHz, and showed a phase noise of -139 dBc/Hz at 1 MHz offset frequency from the carrier across the whole tuning range, for a current consumption of 20 mA with 2.5-V power supply. A figure-of-merit of -190 dBc/Hz is observed.