Wenceslas Rahajandraibe

A new robust over rail to rail comparator based on DCG-FGT transistor

A new comparator based on Dual Control Gate Floating Gate Transistor (DCG-FGT) that allow increasing input voltage range over rail-to-rail is proposed. The comparator operates with a supply voltage ranging from 1.6V to 3.6 V in 90 nm CMOS technology. The comparator is simulated under ELDO and consumes 3.2μA under typical condition.

771mV, 173nA, 90nm CMOS resistorless trimmable voltage reference

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.

A 90-nm CMOS resistor-free compact trimmable voltage reference for ultra-low power low cost applications

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.

A very low phase noise fully integrated CMOS quadrature LC oscillator for 2.4 GHz bluetooth/WLAN applications

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. The QVCO could be tuned between 2.41 and 2.64 GHz, and showed a phase noise of -139 dBc/Hz at 1 MHz offset frequency from the carrier across the whole tuning range, for a current consumption of 20 mA with 2.5-V power supply. A figure-of-merit of -190 dBc/Hz is observed.

Implementation of a readout circuit on SOI technology for the signal conditioning of a neutron detector in harsh environment

A transistor level implementation of the analog block of a readout system on SOI process is presented here. This system is dedicated to the signal conditioning of a neutron detector in harsh environment. The different parts of the readout circuits are defined. The harsh environment constraints (crossing particle effect, high temperatures) are also detailed and modeled in the circuit in order to test and evaluate the characteristics of the designed block when working under these conditions.

A new adaptation scheme for low noise and fast settling phase locked loop

This paper presents a salient analog phase-locked loop that adaptively controls the loop bandwidth according to the locking status. An extended loop bandwidth enhancement is achieved by the adaptive control on the charge pump current. First of all, when the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. The relationships of performance aspects to design variables are presented and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL is described in detail and simulation result of a 50 MHz PLL in a 0.15 mum CMOS technology is presented.

A low-noise fast-settling phase locked loop with loop bandwidth enhancement

A new adaptation scheme for low noise and fast settling 50 MHz analog phase-locked loop (PLL) is presented. According to the locking status, an extended loop bandwidth enhancement is achieved by the adaptive control on the charge pump current . First of all, when the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. The relationships of performance aspects to design variables are presented and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL is described in detail and simulation result of a 50 MHz PLL in a 0:15 mum CMOS technology is presented.

Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling

In modern electronic systems, PLLs are widely used for frequency synthesis applications. PLLs have a mixed analog-digital nature, which makes difficult to characterize its overall non-linear behavior using general theory of feedback system. To simulate the transient behavior of the PLL often the circuit level simulator is used. The frequency divider circuit separates the loop in low and high frequency parts leading to a small sampling time and a high simulation time, which are major technological bottlenecks using behavioral or transistor level models. In this paper, electrical simulations of an arbitrary ordered PLL operating with a voltage switched charge pump (VSCP) are performed. By simulating each block of the VSCP-PLL within the loop using transistor level model, the results were used to setup macroscopic parameters within the Event-Driven model. The Event-Driven simulation efficiently characterizes the off-locking transient domain in a very short time. The Event-Driven simulations are validated by transistor level simulations of arbitrary ordered integer-N VSCP-PLL designed in Cadence (Virtuoso) using CMOS technologies (130nm and 65nm).

Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach

The charge-pump phase locked loop (CP-PLL) is a mostly used integrated circuit (IC) in various modern electronics applications to perform several functions. Due to its mixed analog and digital nature, often circuit level simulators are used to characterize its overall nonlinear dynamic behavior. Since the existing analytical methods are not efficient to account non-ideal and non-linear effects. Furthermore, considering a CP-PLL for frequency synthesis function, a low and high frequency part result in very long simulation times. Consequently, Spice like electrical simulator do not provide a quick assessment of the overall non-linear dynamic behavior of the CP-PLL. Additionally the PVT (Process, Voltage, and Temperature) variations are the most important aspect of the design flow to achieve a robust system. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs (VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the macroscopic behavior and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulations with a good agreement in accuracy and speed-up factor of 60,000 &7,000 for 2nd and 3rd order PLL is achieved respectively.

Exact and approximated discrete-time non-linear models of voltage switched CP-PLL

The charge-pump phase locked loop (CP-PLL) is a mixed signal system and it is a challenging task for a designer to analyze the exact switching behavior of the PLL using any general concept of feedback systems. As the order of the loop filter (LF) is enhanced to cancel pre-filter noise and spurious signals, the more complexity in analysis is inevitable. The PLL operating with a voltage switched charge-pump (VSCP) is a complicated system, since the system representation is not unique in all switching states of the phase and frequency detector (PFD). Therefore, it is not possible to characterize the system with a unique transfer function. In this paper, an exact discrete-time non-linear model of the VSCP-PLL is presented using efficient Event Driven (ED) modeling. By assuming a constant voltage at control node in the zero-state, the approximation model is demonstrated, which can be sufficient to use without complicating the analysis up to some extent. The ED-simulation of the exact model is validated using an equivalent transistor level model designed in 130nm CMOS process. The ability of both exact and approximation model is mapped applying a ramping reference frequency.