Fearghal Morgan

Maintaining Healthy Population Diversity Using Adaptive Crossover, Mutation, and Selection

This paper presents ACROMUSE, a novel genetic algorithm (GA) which adapts crossover, mutation, and selection parameters. ACROMUSEs objective is to create and maintain a diverse population of highly-fit (healthy) individuals, capable of adapting quickly to fitness landscape change and well-suited to the efficient optimization of multimodal fitness landscapes. A new methodology is introduced for determining standard population diversity (SPD) and an original measure of healthy population diversity (HPD) is proposed. The SPD measure is employed to adapt crossover and mutation, while selection pressure is controlled by adapting tournament size according to HPD. In addition to selection pressure control, ACROMUSE tournament selection selects individuals according to healthy diversity contribution rather than fitness. This proposed selection mechanism simultaneously promotes diversity and fitness within the population. The performance of ACROMUSE is evaluated using various multimodal benchmark functions. Statistically significant results are presented comparing ACROMUSEs fitness and diversity performance to that of several other GAs. By maintaining a diverse population of healthy individuals, ACROMUSE responds to fitness landscape change by restoring better fitness scores faster than other GAs. Analysis of the adaptive operators illustrates that the key benefit of ACROMUSE is the synergy of the operators working together to achieve an effective balance between exploration and exploitation.

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.

A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks

FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE), incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

Spiking Neural Networks for Breast Cancer Classification in a Dielectrically Heterogeneous Breast

The considerable overlap in the dielectric properties of benign and malignant tissue at microwave frequencies means that breast tumour classiflcation using traditional UWB Radar imaging algorithms could be very problematic. Several studies have examined the possibility of using the Radar Target Signature (RTS) of a tumour to classify the tumour as either benign or malignant, since the RTS has been shown to be in∞uenced by the size, shape and surface texture of tumours. The main weakness of existing studies is that they mainly consider tumours in a 3D dielectrically homogenous or 2D heterogeneous breast model. In this paper, the efiects of dielectric heterogeneity on a novel Spiking Neural Network (SNN) classifler are examined in terms of both sensitivity and speciflcity, using a 3D dielectrically heterogeneous breast model. The performance of the SNN classifler is compared to an existing LDA classifler. The efiect of combining con∞icting classiflcation readings in a multi-antenna system is also considered. Finally and importantly, misclassifled tumours are analysed and suggestions for future work are discussed.

Xilinx FPGA implementation of an image classifier for object detection applications

This paper describes an FPGA and distributed RAM architecture for an image classifier, implementing object classification stages of an object detection system. The system offers significant performance increase over current programmable DSP-based implementations. The paper shows that the considerable performance improvement using the FPGA solution results from the availability of high I/O resources and pipelined architecture. It also illustrates the suitability of an FPGA solution for tasks (such as real-time video processing) that have a large data throughput and require complex algorithmic manipulations. The system has been implemented using the RC1000-PP Virtex FPGA-based development platform and Handel-C hardware description language.

Hardware spiking neural network prototyping and application

EMBRACE has been proposed as a scalable, reconfigurable, mixed signal, embedded hardware Spiking Neural Network (SNN) device. EMBRACE, which is yet to be realised, targets the issues of area, power and scalability through the use of a low area, low power analogue neuron/synapse cell, and a digital packet-based Network on Chip (NoC) communication architecture. The paper describes the implementation and testing of EMBRACE-FPGA, an FPGA-based hardware SNN prototype. The operation of the NoC inter-neuron communication approach and its ability to support large scale, reconfigurable, highly interconnected SNNs is illustrated. The paper describes an integrated training and configuration platform and an on-chip fitness function, which supports GA-based evolution of SNN parameters. The practicalities of using the SNN development platform and SNN configuration toolset are described. The paper considers the impact of latency jitter noise introduced by the NoC router and the EMBRACE-FPGA processor-based neuron/synapse model on SNN accuracy and evolution time. Benchmark SNN applications are described and results demonstrate the evolution of high quality and robust solutions in the presence of noise. The reconfigurable EMBRACE architecture enables future investigation of adaptive hardware applications and self repair in evolvable hardware.

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.

Exploring the evolution of NoC-based Spiking Neural Networks on FPGAs

Bio-inspired paradigms such as Spiking Neural Networks (SNNs) offer the potential to emulate the repairing and adaptive ability of the brain. This paper presents EMBRACE-FPGA, a scalable, configurable Network on Chip (NoC)-based SNN architecture, implemented on Xilinx Virtex II-Pro FPGA hardware. In association with a Genetic Algorithm-based hardware evolution platform, EMBRACE-FPGA provides a computing platform for intrinsic hardware evolution, which can be used to explore the evolution and adaptive capabilities of hardware SNNs. Results demonstrate the application of the hardware SNN evolution platform to solve the XOR benchmark problem.

SeReCon: a secure reconfiguration controller for self-reconfigurable systems

A risk of covert insertion of circuitry into reconfigurable computing (RC) systems exists. This paper reviews risks of hardware attack on field programmable gate array (FPGA)-based RC systems and proposes a method for secure system credentials generation (unique, random and partially anonymous) and trusted self-reconfiguration, using a secure reconfiguration controller (SeReCon) and partial reconfiguration (PR). SeReCon provides a root of trust (RoT) for RC systems, incorporating novel algorithms for security credentials generation and trusted design verification. Credentials are generated internally, during system certification. The private credential element never leaves the SeReCon security perimeter. To provide integrity-maintaining self-reconfiguration, SeReCon performs analysis of each new IP core structure prior to reconfiguration. An unverified IP core can be used provided that its spatial isolation is retained. SeReCon provides encrypted storage for installed IP cores. Resource usage for a prototype SeReCon system is presented. The protection provided by SeReCon is illustrated in a number of security attack scenarios.

A preliminary study of using wireless kinematic sensors to identify basic Activities of Daily Living

The objective of this on-going work is to evaluate the accuracy and reliability of wireless kinematic sensors in identifying basic Activities of Daily Living (ADL).