Frank Callaly

Home Networking Middleware Infrastructure for Improved Audio/Video Appliance Functionality and Interoperability

A software architecture is described which significantly improves the accessability of multiple home appliances on a heterogeneous home network. Methods for aggregating devices into virtual clusters on a local middleware server are described. These metadevices combine the functionalities of multiple devices but are presented to the user as a single device with a single user interface. Some practical examples of working A/V metadevices are given

Rapid Prototyping of Networked A/V CE Appliances

In this paper the design and rapid prototyping of networked A/V CE appliances is described. Practical implementations of three types of appliance are described: (i) a streaming A/V server; (ii) a streaming A/V client device and (iii) a networked A/V transcoding device. It is shown how these devices can be used to provide both a robust and scalable multimedia solution, which can be adapted for use in many applications. A review of known techniques for realizing the required multimedia functionality is given and some methods of reducing the development time of these prototypes are also discussed

Remote FPGA Lab with Interactive Control and Visualisation Interface

This paper describes a scalable and extendable Remote Field Programmable Gate Array Laboratory (Remote FPGA) which can be used to enhance the learning of digital systems and FPGA applications. The web-based console provides an always-on, real-time, interactive control and visualisation interface to/from a bank of remote FPGAs. A Xilinx ISE project template enables integration of user HDL-based designs to execute on the Remote FPGA. Host-FPGA communication is supported using a register-based interface. Users can create real-time, interactive and visual demonstrators of digital systems components. The paper presents a demonstrator for a Finite State Machine (FSM) application, and illustrates the use of web-based control and visualisation for enhanced learning of FSM behaviour. The paper also presents a case study of the use of Remote FPGA in undergraduate teaching.

Real-Time Fingerprint Analysis & Authentication for Embedded Appliances

A complete fingerprint analysis system is described. The design and architecture of a loadable device driver for a USB fingerprint sensor is described. Image processing filters to enhance the raw image data and to extract key points from fingerprint images are also described. Finally a novel pattern matching technique which allows fast authentication is described. The results of initial reliability testing and some example applications of fingerprint authentication in CE appliances are given.

Exploring Neural Principles with Si elegans, a Neuromimetic Representation of the Nematode Caenorhabditis elegans

Biological neural systems are powerful, robust and highly adaptive computational entities that outperformconventional computers in almost all aspects of sensory-motor integration. Despite dramatic progress ininformation technology, there is a big performance discrepancy between artificial computational systemsand brains in seemingly simple orientation and navigation tasks. In fact, no system exists that can faithfullyreproduce the rich behavioural repertoire of the tiny worm Caenorhabditis elegans which features one of thesimplest nervous systems in nature made of 302 neurons and about 8000 connections. The Si elegans projectaims at providing this missing link. This article is sketching out the main platform components.

The Si elegans Project – The Challenges and Prospects of Emulating Caenorhabditis elegans

Caenorhabditis elegans features one of the simplest nervous systems in nature, yet its biological information processing still evades our complete understanding. The position of its 302 neurons and almost its entire connectome has been mapped. However, there is only sparse knowledge on how its nervous system codes for its rich behavioral repertoire. The EU-funded Si elegans project aims at reverse-engineering C. elegans‘ nervous system function by its emulation. 302 in parallel interconnected field-programmable gate array (FPGA) neurons will interact through their sensory and motor neurons with a biophysically accurate soft-body representation of the nematode in a virtual behavioral arena. Each FPGA will feature its own reprogrammable neural response model that researchers world-wide will be able to modify to test their neuroscientific hypotheses. In a closed-feedback loop, any sensory experience of the virtual nematode in its virtual environment will be processed by sensory and subsequently interconnected neurons to result in motor commands at neuromuscular junctions at the hardware-software interface to actuate virtual muscles of the virtual nematode. Postural changes in the virtual world will lead to a new sensory experience and thus close the loop. In this contribution we present the overall concepts with special focus on the virtual embodiment of the nematode. For further information and recent news please visit http://www.si-elegans.eu.

Neuron Models in FPGA Hardware - A Route from High Level Descriptions to Hardware Implementations

This paper presents the LEMS2HDL toolsuite which converts Low Entropy Model Specification (LEMS) neuron/neural network models to synthesisable Hardware Description Language (HDL) hardware descriptions. The LEMS2HDL process will provide a route for the neuroscience community to perform accelerated Field-Programmable Gate Array (FPGA) hardware implementations of the growing library of LEMS neuron/neural network models. The paper describes the LEMS to HDL conversion process and references the previously reported vicilogic platform. The paper compares the resulting FPGA hardware simulation of three LEMS neuron models with the LEMS model simulation.

Web-enabled Neuron Model Hardware Implementation and Testing.

This paper presents a prototype web-based Graphical User Interface (GUI) platform for integrating and testing a system that can perform Low-Entropy Model Specification (LEMS) neural network description to Hardware Description Language (VHDL) conversion, and automatic synthesis and neuron implementation and testing on Field Programmable Gate Array (FPGA) testbed hardware. This system enables hardware implementation of neuron components and their connection in a small neural network testbed. This system incorporates functionality for automatic LEMS to synthesisable VHDL translation, automatic VHDL integration with FPGA logic to enable data I/O, automatic FPGA bitfile generation using Xilinx PlanAhead, automated multiFPGA testbed configuration, neural network parameter configuration and flexible testing of FPGA based neuron models. The prototype UI supports clock step control and real-time monitoring of internal signals. References are provided to video demonstrations.

Managing Digital Image Collections from your TV-Set: A State-of-Art Review

The problem of managing growing digital image collections is discussed in the context of a home user. The use of a conventional television set as both a viewing and management tool is discussed. The problem of linking digital cameras and other networked computer devices is outlined. A review of recent technological approaches to integrating the TV set with digital assets such as image collections is given. An overview of emerging TV-centric solutions is also given followed by a discussion of the potential merits of open standards for home networks and content based tools and services.

Fast A/V Channel Switching on a Wireless Home Network

A method of enabling fast switching between multimedia streams on an 802.11g network is described. This technique is particularly useful for A/V home network applications where it is desirable to simulate the fast channel switching of conventional analog TV channels in order to emulate the behaviour of multichannel TV