Feifei He

Circuit level interconnect reliability study using 3D circuit model

Integrated circuit (IC) reliability is gaining increasing concerns in IC technology with decreasing device size, and the impact of interconnect failure mechanisms on IC failure rate increases significantly with decreasing interconnect dimension and increasing number of interconnect levels. In this work, we attempt a first step in the study of interconnect electromigration reliability in integrated circuit using a complete 3D circuit model. 3D circuit model is necessary because all integrated circuits are 3D in their actual physical implementation, and 3D model is essential for the study of today interconnect reliability. As temperature and stress distributions in the interconnect are crucial to its reliability, we demonstrate our method through the computation of their distributions in a simple inverter circuit under typical normal operating condition, and the locations of the electromigration weak spots in the interconnect system are identified.

3D circuit model for 3D IC reliability study

3D integrated circuit technology is an emerging technology for the near future, and has received tremendous attention in the semiconductor community. With the 3D integrated circuit, the temperature and thermo-mechanical stress in the various parts of the IC are highly dependent on the surrounding materials and their materials properties, including their thermal conductivities, thermal expansivities, Young modulus, poisson ratio etc. Also, the architectural of the 3D IC will also affect the current density, temperature and thermo-mechanical stress distributions in the IC. In view of the above-mentioned, the electrical-thermal-mechanical modeling of integrated circuit can no longer be done with a simple 2D model. The distributions of the current density, temperature and stress are important in determining the reliability of an IC. In this work, we demonstrate a method of converting 2D circuit layout into a 3D model. Simulations under real circuit operating condition are carried out using both Cadence (a circuit simulator) and ANSYS (finite element tool). Limiting our study to the electromigration failure, we compute the current density, temperature and stress distributions of the interconnect layers by considering the heat transfer and Joule heating, and the “weak spot” for electromigration is identified. Layout design can be modified based on the simulation results so as to enhance the 3D circuit interconnect reliability.

Rapid ULSI Interconnect Reliability Analysis Using Neural Networks

Neural network modeling method is introduced for analyzing ultralarge scale integration (ULSI) interconnect reliability for the first time. By training the simulation data from ANSYS (a finite-element tool), a neural network model is developed, where the prediction of ULSI interconnect reliability can be more effectively done. The proposed technique is useful for integrated circuit design since it can produce a database of interconnect layouts with reliability comparison for a given circuit. From the database, we can know the relative reliability of interconnect layout at any given temperature or current rapidly. Through this proposed technique, we can also derive the allowable temperature and current range of a circuit to ensure given reliability criteria.

Effect of IC layout on the reliability of CMOS amplifiers

Abstract With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.

Degradation behavior of high power light emitting diode under high frequency switching

Abstract Visual Light Communication (VLC) is a system that uses light wavelengths that is not injurious to the eye for communication purposes. This system provides a solution to some technological problems such as the increasingly limited availability of conventional bandwidths for electronic equipment. Recent development in solid-state lighting (SSL) allows it to be highly efficient, longer life time and versatile. These advantages made SSL to be highly acceptable by the public and are slowly replacing the conventional fluorescent lamps. The improvement and acceptability of the solid-state lighting allows a great advancement in the development of VLC. However, the focus of the development of SSL has been for lighting purposes and not for VLC system. This work investigate the degradation behavior of SSL under switching condition with various stress condition such as temperature, frequency, modulation index so as to provide the feasibility of the use of SSL for VLC.

Investigation of work function and surface energy of aluminum: An ab-initio study

The work function and surface energy of aluminum with different orientations are investigated by employing the DFT simulation. We mainly focus on two situations: pure aluminum surface and aluminum surface with impurities. The numerical results indicate that the work function of Al (100) is larger than Al (110). With the introduction of the impurities (carbon atoms), the work function increases because of the extra electric dipoles on the surface. We also find that the surface energy of Al (100) is smaller than that of Al (110) indicating that Al (100) surface is more stable. When there are impurities on the surface, the surface energy decreases for silicon impurity and increases for calcium impurity. The magnitude of the increase is related to the orientation of the surface.

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

The continuous scaling down of the device size and escalating circuit speed drives the requirement for EM-resistant Cu interconnect with diffusion barrier and the low-k dielectric. The study of barrier layer thickness and low-k dielectric effect in a complete 3D circuit is necessary as the actual physical implementation of an integrated circuit in a wafer is indeed 3D in nature. This paper investigates the effect of barrier layer thickness and low-k dielectric on the circuit reliability of a complete 3D circuit model. It was found that the maximum atomic flux divergence (AFD) value increases with decreasing barrier layer thickness, which implied a shorter EM lifetime with thinner barrier. Low-k dielectric will give a higher maximum AFD due to higher stress gradient, and thus a shorter EM lifetime.

Predicting Integrated Circuit Reliability from Wafer Fabrication Technology Reliability Data

A reliability tool is developed to predict integrated circuit reliability simply from the wafer fabrication or foundry technology reliability test data, considering the various failure mechanisms acting simultaneously during the operation of an IC. The reliability of an IC as a function of operation time can be obtained, and the mean time to failure as well as the medium time to failure can be predicted before the IC is fabricated. An example of the application of the tool to 6T SRAM is used for the demonstration. The distribution of the failure mechanisms in the SRAM cell at different operation time can also be determined. This distribution helps us to identify the probably root causes for the early failure of the SRAM so that reliability improvement effort can be focused and effective. It is also shown that the reliability of the SRAM of different memory size can be very different even the fabrication technology reliability and the cell design remain unchanged.

Ab initio simulation of electronic and mechanical properties of aluminium for fatigue early feature investigation

Fatigue crack initiation and propagation are the central issues for understanding fatigue behaviours, and early detection of fatigue will be useful in industry before cartographic events occur. It has been found that surface work function, Youngs modulus and surface energy are inter-dependent with the occurrence of fatigue, and we compute these material properties using ab intio simulation for aluminium. We found that the highest work function represents stability of the surface with respect to fatigue, and that the closest-packed (111) face has the highest work function. Also, the work function with C impurities is higher than that without C impurities for all orientations of Al, indicating that C impurities can help to stabilise the surface. Surface work function is also found to be dependent on the surface roughness, and the dependence varies with Al orientations. In particular, the work functions of the closest-packed Al (111) and Al (100) decrease as roughness increases. However, for Al (110), the work function increases with roughness, and the different dependences on roughness require further study in order for work function to be used to detect the potential site of fatigue as well as the initiation of fatigue. Lower surface energy indicates a more stable surface from fatigue as most cracks initiate from the surface. Our calculation shows that Al surface energy decreases with the existence of Si impurities but increases slightly with that of Ca impurities, showing the importance of surface impurities in affecting fatigue early behaviours. It has been shown that Youngs modulus decreases with fatigue cycles and when a low threshold is reached, cracks will be initiated. We find that the Youngs modulus of Al (111) is the largest, indicating its robustness against fatigue as compare to other orientations.