Felipe A. P. de Figueiredo

Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE

This paper presents a configurable and optimized hardware architecture for computing Zadoff-Chu (ZC) complex sequences in the frequency domain. It is a hardware-efficient and accurate architecture for computing ZC sequences in realtime. The architecture is mainly based on the CORDIC algorithm for computing complex exponentials using only shift and add operations. Due to transformations applied to the Zadoff-Chu equation it is possible to eliminate the use of multipliers with non-constant terms. This hardware architecture is employed by the Physical Random Access Channel (PRACH) in LTE and LTE-A systems during the reception and detection of random access preambles. Its main advantage is that it eliminates the need for storing a large number of long complex ZC sequences. Simulation results show that the proposed architecture is accurate, efficient and renders the resulting PRACH receiver fully compliant with 3GPPs detection requirements.

Code block segmentation hardware architecture for LTE-Advanced

A very efficient algorithm and hardware architecture for code block segmentation used on LTE-Advanced channel coding physical layer (PHY) is presented in this paper. Code block segmentation is a generic procedure which is commonly applied before turbo encoding. Its main function is to fragment a large transport block into smaller code blocks. This approach reduces memory requirements of the turbo code interleaver, without compromising its coding gain, since turbo encoder improves its performance as the size of the code block increases. The current work presents not only an optimized procedure with reduced computational complexity, but also an architecture with very low resource count, regarding ASIC or FPGA implementations, performing at a maximum frequency of 351 MHz on a FPGA architecture.

On the performance of code block segmentation for LTE-advanced

In this paper we present a new approach to code block segmentation used on the 3GPP Standard LTE-Advanced channel coding physical layer. Code block segmentation is a generic procedure commonly applied before turbo encoding whose sole function is to fragment a large transport block into smaller code blocks, reducing memory requirements of the turbo code interleaver. The main result of this paper is a speedup of 80 times over the original procedure defined by the 3GPP Std. when implemented in a DSP architecture.

A modified CA-CFAR method for LTE random access detection

Random Access is an important aspect of mobile systems where multiple users are always competing for resources. However, noise imposes a significant problem to those systems causing them to falsely detect access requests. In consequence, unnecessary processing and air traffic are generated based upon these unreal request events. This paper presents a modified Cell-Average Constant False Alarm Rate (CA-CFAR) strategy used for random access detection of CAZAC preambles in the presence of noise. Simulation results indicate that the proposed method performs well even in the case of low SNR.

Radio Hardware Virtualization for Coping with Dynamic Heterogeneous Wireless Environments.

Diverse wireless standards, designed for diverse traffic types, operate in the same wireless environment without coordination, often leading to interference and inefficient spectrum usage. Although C-RAN (Cloud/centralized RAN) is a promising architecture to achieve intra-operator network coordination, the architecture encounters challenge when low latency services and diverse access technologies are expected over non-fiber fronthaul. So, multi-standard multi-channel access point with low processing latency is preferred to be at the edge of network instead of central cloud. But, developing this kind of equipment is difficult as multiple radio chips and drivers have to be integrated and coordinated. In ORCA (Orchestration and Reconfiguration Control Architecture) project, a SDR architecture is developed on a single chip radio platform including hardware accelerators wrapped by unified software APIs, which offer the following capabilities: (1) concurrent data transmission over multiple virtual radios; (2) runtime composition and parametric control of radios; and (3) radio resource slicing, supporting independent operation of multiple standards in different bands, time slots or beams. Such an architecture offers a fast development cycle, as only software programming is required for creating and manipulating multiple radios. The architecture further achieves an efficient utilization of hardware resources, as accelerators can be shared by multiple virtual radios.

Channel Estimation for Massive MIMO TDD Systems Assuming Pilot Contamination and Frequency Selective Fading

Channel estimation is crucial for massive multiple-input multiple-output (MIMO) systems to scale up multi-user MIMO, providing significant improvement in spectral and energy efficiency. In this paper, we present a simple and practical channel estimator for multipath multi-cell massive MIMO time division duplex systems with pilot contamination, which poses significant challenges to channel estimation. The proposed estimator addresses performance under moderate to strong pilot contamination without previous knowledge of the inter-cell large-scale fading coefficients and noise power. Additionally, we derive and assess an approximate analytical mean square error (MSE) expression for the proposed channel estimator. We show through simulations that the proposed estimator performs asymptotically as well as the minimum MSE estimator with respect to the number of antennas and multipath coefficients.

Efficient Frequency Domain Zadoff-Chu generator with application to LTE and LTE-A systems

This paper presents a configurable and optimized hardware architecture for computing Zadoff-Chu (ZC) complex sequences in the Frequency Domain (FD). It is a hardware-efficient and accurate architecture for computing ZC sequences in real-time. The architecture is mainly based on the CORDIC algorithm for computing complex exponentials using only shift and add operations. Due to transformations applied to the Zadoff-Chu equation it is possible to eliminate the use of multipliers with non-constant terms. This hardware architecture is employed by the Physical Random Access Channel (PRACH) in LTE and LTE-A systems during the reception and detection of random access preambles. Its main advantage is that it eliminates the need for storing a large number of long complex ZC sequences.

FPGA design and implementation of Digital Up-Converter using quadrature oscillator

In this paper we design and implement a complex Digital Up-Converter (DUC) using a Xilinx Virtex6 FPGA. All the steps necessary to build such circuits are thoroughly described and some valuable hints on how to overcome problems during the design time are presented. We introduce a new approach for oscillator circuits, which are an important part of any DUC design. Such oscillator approach is stable, clean, accurate and easily tunable. It is also RAM memory efficient, consuming no block RAM and a small amount of logic.

A Framework for the Automation of LTE Physical Layer Tests

The long term evolution (LTE) network architecture comprises, among other elements, the base station (eNodeB), which provides and controls the air interface. eNodeB protocol stack is composed of different layers, each one with specific purpose. In terms of air interface performance, the most critical layers of an eNodeB are the physical layer (PHY) and the medium access control layer (MAC). Both must operate on precise timing basis, corresponding to a frame duration of 1 ms. Because of this requirement, PHY layer developers need an effective test architecture, capable to follow time response policies. This article proposes an automated test framework for eNodeB’s physical layer development, comprising procedures for checking data integrity, stability and performance. This framework is based on a simplified LTE MAC layer, which operates as a software element that communicates directly with the physical layer and performs mapping procedures between logical and physical channels, reception and transmission of physical layer data, user data scheduling and data exchange with mobile terminals. All above mentioned procedures are performed with no further dependency on other LTE network elements, thus providing a stand-alone test framework.

Radio Hardware Virtualization for Software-Defined Wireless Networks

Software-Defined Network (SDN) is a promising architecture for next generation Internet. SDN can achieve Network Function Virtualization much more efficiently than conventional architectures by splitting the data and control planes. Though SDN emerged first in wired network, its wireless counterpart Software-Defined Wireless Network (SDWN) also attracted an increasing amount of interest in the recent years. Wireless networks have some distinct characteristics compared to the wired networks due to the wireless channel dynamics. Therefore, network controllers present some extra degrees of freedom, such as taking measurements against interference and noise, or adapting channels according to the radio spectrum occupation. These specific characteristics bring about more challenges to wireless SDNs. Currently, SDWN implementations are mainly using customized firmware, such as OpenWRT, running on an embedded application processor in commercial WiFi chips, and restricted to layers above lower Media Access Control. This limitation comes from the fact that radio hardware usually require specific drivers, which have a proprietary implementation by various chipset vendors. Hence, it is difficult, if not impossible, to achieve virtualization on the radio hardware. However, this status has been changing as Software-Defined Radio (SDR) systems open up the entire radio communication stack to radio hobbyists and researchers. The bridge between SDR and SDN will make it possible to bring the softwarization and virtualization of wireless networks down to the physical layer, which will unlock the full potential of SDWN. This paper investigates the necessity and feasibility of extending the virtualization of wireless networks towards the radio hardware. A SDR architecture is presented for radio hardware virtualization in order to facilitate SDWN design and experimentation. We do believe that by adopting the virtualization-oriented hardware accelerator design presented here, an all-layer end-to-end high performance SDWN can be achieved.