Karlo G. Lenzi

Introduction to the Software-defined Radio Approach

Telecommunications have been in constant evolution during past decades. Among the technological innovations, the use of digital technologies is very relevant. Digital communication systems have proven their efficiency and brought a new element in the chain of signal transmitting and receiving, the digital processor. This device offers to new radio equipments the flexibility of a programmable system. Nowadays, the behavior of a communication system can be modified by simply changing its software. This gave rising to a new radio model called Software Defined Radio (or Software-Defined Radio - SDR). In this new model, one moves to the software the task to set radio behavior, leaving to hardware only the implementation of RF front-end. Thus, the radio is no longer static, defined by their circuits and becomes a dynamic element, which may change their operating characteristics, such as bandwidth, modulation, coding rate, even modified during runtime according to software configuration. This article aims to present the use of GNU Radio software, an open-source solution for SDR specific applications, as a tool for development configurable digital radio.

Software defined radio on digital communications: A new teaching tool

In this paper we present a Software Defined Radio (SDR) platform, composed by a USRP hardware and GNU Radio, as a new approach for teaching telecommunications at schools of Electrical Engineering. The proposed approach makes the preparation of an experiment faster by using modern communications architectures, which significantly reduce the occurrence of errors during the setup of test beds as well. This gives the students the opportunity to focus their efforts on the learning of communications techniques and algorithms. Furthermore, we intend to make easier the verification and validation processes of implemented models, supported by the use of specialized tools.

Performance Measurement Simulations for Analog-to-Digital Converters

This paper concisely presents several common used techniques for measuring the dynamic performance of analog-to-digital conversion. Details about very critical tasks concerning spectral analysis are focused, showing examples to better justify the use of such techniques. It is shown how important is to precisely define the input frequency used for spectral analysis to enhance precision of results. This paper also proposes that the use of window deconvolution eases computation of the harmonics for performance analysis as compared with other commonly used techniques. The most relevant metrics applied for measuring performance are reviewed and demonstrated as a self-contained study. Simulation results are confronted with a commercial analog-to-digital converter.

Code block segmentation hardware architecture for LTE-Advanced

A very efficient algorithm and hardware architecture for code block segmentation used on LTE-Advanced channel coding physical layer (PHY) is presented in this paper. Code block segmentation is a generic procedure which is commonly applied before turbo encoding. Its main function is to fragment a large transport block into smaller code blocks. This approach reduces memory requirements of the turbo code interleaver, without compromising its coding gain, since turbo encoder improves its performance as the size of the code block increases. The current work presents not only an optimized procedure with reduced computational complexity, but also an architecture with very low resource count, regarding ASIC or FPGA implementations, performing at a maximum frequency of 351 MHz on a FPGA architecture.

On the performance of code block segmentation for LTE-advanced

In this paper we present a new approach to code block segmentation used on the 3GPP Standard LTE-Advanced channel coding physical layer. Code block segmentation is a generic procedure commonly applied before turbo encoding whose sole function is to fragment a large transport block into smaller code blocks, reducing memory requirements of the turbo code interleaver. The main result of this paper is a speedup of 80 times over the original procedure defined by the 3GPP Std. when implemented in a DSP architecture.

A modified CA-CFAR method for LTE random access detection

Random Access is an important aspect of mobile systems where multiple users are always competing for resources. However, noise imposes a significant problem to those systems causing them to falsely detect access requests. In consequence, unnecessary processing and air traffic are generated based upon these unreal request events. This paper presents a modified Cell-Average Constant False Alarm Rate (CA-CFAR) strategy used for random access detection of CAZAC preambles in the presence of noise. Simulation results indicate that the proposed method performs well even in the case of low SNR.

FPGA design and implementation of Digital Up-Converter using quadrature oscillator

In this paper we design and implement a complex Digital Up-Converter (DUC) using a Xilinx Virtex6 FPGA. All the steps necessary to build such circuits are thoroughly described and some valuable hints on how to overcome problems during the design time are presented. We introduce a new approach for oscillator circuits, which are an important part of any DUC design. Such oscillator approach is stable, clean, accurate and easily tunable. It is also RAM memory efficient, consuming no block RAM and a small amount of logic.

Optimized Math Functions for a Fixed-Point DSP Architecture

The identification of replicas in a database is fundamental to improve the quality of the information. Deduplication is the task of identifying replicas in a database that refer to the same real world entity. This process is not always trivial, because data may be corrupted during their gathering, storing or even manipulation. Problems such as misspelled names, data truncation, data input in a wrong format, lack of conventions (like how to abbreviate a name), missing data or even fraud may lead to the insertion of replicas in a database. The deduplication process may be very hard, if not impossible, to be performed manually, since actual databases may have hundreds of millions of records. In this paper, we present our parallel deduplication algorithm, called FER- APARDA. By using probabilistic record linkage, we were able to successfully detect replicas in synthetic datasets with more than 1 million records in about 7 minutes using a 20- computer cluster, achieving an almost linear speedup. We believe that our results do not have similar in the literature when it comes to the size of the data set and the processing time.This paper presents a method for implementing several high-performance math functions through polynomial approximation on the fixed-point Blackfin ADSP-BF533 architecture. We present a strategy to overcome the performance given by the Blackfin s C library using a fast emulated floating-point format. We also discuss the methods applied to generate the polynomial approximation for the sine, logarithmic, and exponential functions, as well as the optimization schemes used to implement these functions. This work contributed to a maximum cycle reduction of 85% over the standard math library.

LTE-Advanced channel coding generic procedures A high-level model to guide low-level implementations

This paper presents a high-level functional model for the 3GPP LTE-Advanced channel coding generic procedures. Due to the complexity of modern wireless communication systems, it is fundamental to have a well-defined high-level model to guide low-level implementations, like C/C++ or HDL. Highlevel modeling not only serves the purpose of proving the correctness of a given system, but also to present measures of its optimal performance, since we are not yet restricted by any technology. The LTE-Advanced channel coding is composed by five generic procedures: CRC calculation, code block segmentation and CRC attachment, channel coding, rate matching and code block concatenation. The aggregation of these procedures creates the great majority of the downlink and uplink transport channels. In this paper, we present a very simple way of modeling the channel coding, offering a reference for future LTE channel coding developments.

On the Performance of Code Block Segmentation for LTE-Advanced: An In-Depth Analysis

In this paper we present a new approach to code block segmentation used on the 3GPP Standard LTE-Advanced channel coding physical layer. Code block segmentation is a generic procedure commonly applied before turbo encoding whose sole function is to fragment a large transport block into smaller code blocks, reducing memory requirements of the turbo code interleaver. The main result of this paper is a speedup of 80 times over the original procedure defined by the 3GPP Std. when implemented in a DSP architecture.