Felix Mühlbauer

Design Space Exploration for the BLAST Algorithm Implementation

The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board co-design to solve these issues.This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, we introduce a general polynomial approximation approach with an adaptive divide-in-halves segmentation method for evaluation of LNS arithmetic functions. Second, we develop a library generator that automatically generates optimized LNS arithmetic units with a wide bit-width range from 21 to 64 bits, to support LNS application development and design exploration. The basic arithmetic units are tested on practical FPGA boards as well as software simulation. When compared with existing LNS designs, our generated units provide in most cases 6% to 37% reduction in area and 20% to 50% reduction in latency. The key challenge for LNS remains on the application level. We show the performance of LNS versus floating-point for realistic applications: digital sine/cosine waveform generator, matrix multiplication and radiative Monte Carlo simulation. Our infrastructure for fast prototyping LNS FPGA applications allows us to efficiently study LNS number representation and its tradeoffs in speed and size when compared with floating-point designs.

A dynamic reconfigurable hardware/software architecture for object tracking in video streams

This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

Design and Implementation of an Object Tracker on a Reconfigurable System on Chip

This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management as well as an efficient use of memory and processor features. The implementation is done on a Xilinx evaluation board and the results provided show the superiority of our implementation compared to the other works

Auto-reconfiguration on self-organized intelligent platform

This paper proposes a new approach for the utilization of reconfigurable hardware in a self-organized context. A concept and a system are presented under the form of Reconfigurable Self-Organized Systems (RSS). The goal is to study the impact of FPGA based systems in a self-organized networked environment. Partial Reconfiguration is used to implement hardware accelerators at runtime. The proposed system is designed to study at each level, parameters that influence performance. As results, first timing measurements of partial reconfiguration are proposed. They are seen from the software point of view and show effects of partial reconfiguration technology on the general performance of RSS.

SoPC Architecture for a Key Point Detector

The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board to solve these issues.

Rapid prototyping of OpenCV image processing applications using ASP

Image processing is becoming more and more present in our everyday life. With the requirements of miniaturization, low-power, performance in order to provide some intelligent processing directly into the camera, embedded camera will dominate the image processing landscape in the future. While the common approach of developing such embedded systems is to use sequentially operating processors, image processing algorithms are inherently parallel, thus hardware devices like FP-GAs provide a perfect match to develop highly efficient systems. Unfortunately hardware development is more difficult and there are less experts available compared to software. Automatizing the design process will leverage the existing infrastructure, thus providing faster time to market and quick investigation of new algorithms. We exploit ASP (answer set programming) for system synthesis with the goal of genarating an optimal hardware software partitioning, a viable communication structure and the corresponding scheduling, from an image processing application.

On hardware-based fault-handling in dynamically scheduled processors

This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e. g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.

Feasibility of software-based repair for program memories

In this paper we evaluate the feasibility of software-based repair for program (NOR flash) memories in tiny embedded systems. Often, in such systems, it is very typical that not the full memory area is used by the application. This paper proposes a software-based self-repair for program memories which utilizes this inherently available redundancy. Our techniques combine application adaptation in respect to faulty memory words and protection of the adapted application with error-correcting code. With our approach we address post-production memory faults and retention- and radiation-related memory faults which can occur in the field. The evaluation of our repair mechanisms was based on the results from post-production and after burn-in tests performed on real 32 and 64 KByte flash memory devices.

Handling of permanent faults in dynamically scheduled processors

This paper presents and evaluates a hybrid fault tolerance approach for dynamically scheduled processors that combines on-line error-correction for run-time fault handling with reconfiguration techniques for permanent fault handling. A permanent reconfiguration is triggered on-demand during runtime, depending on the frequency of on-line corrected faults. The presented work evaluates the effect of the permanent reconfiguration regarding the reliability and performance impact. It turns out that only in few cases the on-line handling of permanent faults performs better than the reconfiguration-mechanism.

Enabling self-organization in embedded systems with reconfigurable hardware

We present a methodology based on self-organization to manage resources in networked embedded systems based on reconfigurable hardware. Two points are detailed in this paper, the monitoring system used to analyse the system and the Local Marketplaces Global Symbiosis (LMGS) concept defined for self-organization of dynamically reconfigurable nodes.