Mario Schölzel

Software-based self-repair of statically scheduled superscalar data paths

This paper describes a purely software-based approach to handle permanent faults in the data path of a statically scheduled superscalar processor architecture; e.g. a VLIW processor. This approach does not need any hardware in the processor core itself to reconfigure the data path. Rather the reconfiguration is done in software by modifying the binary code in the program memory of the processor. By this, the usage of a faulty component in the data path can be avoided during the execution of the program. The modification of the program is carried out by a repair routine that is executed by the faulty processor itself. It is shown that this is possible even if there is a fault in the data path. The modification of the binary code takes place immediately after a software-based self-test. Both, the self-test and the modification are carried out immediately after the start-up of the system. Thus, the detection and repair of a fault can happen in the field. Furthermore, the compiler must generate the program in a special way in order to guarantee that the binary code can be modified under all specified fault situations. A simple scheduling algorithm that produces such fault-tolerant binary code is presented, too.

On the Feasibility of Built-In Self Repair for Logic Circuits

According to recent investigations on fault mechanisms in nano-scale integrated circuits, they suffer from wear-out effects that limit their life time seriously. For applications that combine a long life time and safety-critical functionality, means of fault compensation, de-stressing and eventual self repair are therefore becoming a must. This paper presents a circuit architecture that combines capabilities of self repair and de-stressing for logic circuits. Circuits that administrate repair functions are introduced. The necessary overhead for redundancy as well as for circuit re-organization is shown, depending on the granularity of repair. Finally limitations as well as single points of failure are discussed.

HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths

This paper describes a hardware-/software-based technique to make the data path of a statically scheduled super scalar processor fault tolerant. The results of concurrently executed operations can be compared with little hardware overhead in order to detect a transient or permanent fault. Furthermore, the hardware extension allows to recover from a fault within one to two clock cycles and to distinguish between transient and permanent faults. If a permanent fault was detected, this fault is masked for the rest of the program execution such that no further time is needed for recovering from that fault. The proposed extensions were implemented in the data path of a simple VLIW processor in order to prove the feasibility and to determine the hardware overhead. Finally a reliability analysis is presented. It shows that for medium and large scaled data paths our extension provides an up to 98% better reliability than triple modular redundancy.

DESCOMP: a new design space exploration approach

In this paper, we introduce a new approach in Design-Space-Exploration (DSE) for non-clustered VLIW architectures. It differs from existing techniques by using a “bottom-up” strategy. While other approaches start with the design of an architecture, followed by building a possible schedule, we firstly build a schedule and after that an architecture is synthesized, which is suitable to execute this schedule. So, the results can be obtained fully automatically and in very short time. Furthermore, we can explore arbitrary types of functional units without increasing the design space exploration time significantly. We evaluated our method and compared the obtained results to an existing DSE approach for clustered and non-clustered architectures. We almost always obtain better results in the case of non-clustered architectures. In many cases the ports of the register file are decreased, which, in consequence, leads to higher clock rates. Compared to the results for clustered architectures for some examples our non-clustered architecture is better than the best clustered one.

A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors

This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques, a combination of them in a hierarchical manner is provided. By this, the data path of the VLIW processor can be checked within a very short time and at a fine grained diagnostic level. The results show that the required diagnostic resolution for the used processor model with self-repair capability can be obtained with a relatively small hardware overhead of about 6%.

Fine-Grained Software-Based Self-Repair of VLIW Processors

This paper describes a fine-grained software-based self-repair method for statically scheduled super scalar processors. An important property of this processor type is that for each operation of the executed program it is known in advance, which resources of the processor will be used by that operation. A scheduling algorithm is introduced that employs this knowledge in order to rearrange the operations in a VLIW program in the field in such a way that components with permanent faults are no longer used. It is explained, how the scheduling algorithm bypasses these failure points such that the affected components can be used partially, even if they contain some permanent faults. The fine-grained self-repair approach is compared with state-of-the art coarse-grained approaches. It turns out that the number of systems that are still running after injecting 10 faults is about 80%, while less than 1% of these systems will survive if a coarse-grained approach is used.

Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths

This paper describes hardware- and software-based self-repair methods and how to combine them in order to obtain hybrid methods. All presented methods are able to handle multiple permanent faults in processors with a statically scheduled data path, e.g. a VLIW processor. They are based on adapting the executed program in the field to the current fault situation. The first method is a simple hardware-based technique. It binds dynamically operations to other execution units. A recently published first software-based method is briefly described, and a new second software-based method is introduced to overcome some weaknesses of the first one. Two hybrid methods are obtained by combining each software-based method with the hardware-based method. A detailed analysis of the advantages and disadvantages of each method is given. This includes a reliability analysis, the hardware overhead, the repair time, and the effect of multiple faults on the runtime of an executed application.

Reduced Triple Modular redundancy for built-in self-repair in VLIW-processors

In this paper we propose a new idea for built-in-self-repair of application specific VLIW processors, which relies on a special kind of triple modular redundancy, which we call Reduced Triple Modular Redundancy (RTMR). The key idea is to employ the redundancy of operators in the data path of a VLIW processor. I.e., every operation is executed twice by two different operators during normal program execution. Only in case a mismatch between both computed results occurs, the operation is executed by a third operator. Therefore, during most of the execution time, the third operator can be used for executing regular operations of the program. We propose modifications of the VLIW architecture in order to detect a mismatch in computed results. Necessary program transformations are introduced, in order to obtain an internal representation for fault tolerant programs that can be scheduled to the proposed VLIW architecture. Furthermore, we propose the program execution model that is used in case a permanent fault in the data path has been detected and give some preliminary results.

Combining fault tolerance and self repair at minimum cost in power and hardware

Large-scale integrated circuits and systems fabricated in nano-technologies exhibit new and enhanced fault properties which limit both their reliability and their life time. Transient fault effects have found most attention so far. They must be handled by on-line check and fault compensation based on duplication and triplication, typically at a significant amount of extra power. Such techniques are not suitable for life time extension, since their redundant elements all undergo wear-out effects in hot operation. Repair technologies that perform a process of system re-organization and introduction of cold redundancy may extend system life time, but they are too slow to catch and correct transient and permanent fault effects in hot operation. The essential task therefore remains to find methods and architectures that will provide on-line check in combination with self repair techniques at a minimum cost in extra power.

An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores

The localization of permanent faults in a processor is a precondition for applying (self-)repair functions to that processor core. This paper presents a software-based self-test technique that can be used in the field for test and fault localization, there-by providing a high diagnostic resolution. It is shown how the self-test routine is adapted in the field to already detected faults in the processor, such that these faults do not affect the test- and diagnostic capability of the self-test routine. By this it becomes reasonable to localize multiple permanent faults in the processor. The proposed self-test is software-based, but it requires a few modifications of the processor. The feasibility of the technique is presented by an example; limitations are discussed, too.