Felix Palumbo

Dielectric breakdown mechanisms in gate oxides

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient

A physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy (DBIE) formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.

Radiation Tolerance of NROM Embedded Products

Radiation tolerance of NROM memories is demonstrated at the level of industrial 4 Mbit memory embedded modules, specifically not designed for operation in radiation harsh environments. The memory fabricated in 0.18 um technology remains fully functional after total ionization doses exceeding 100 krad. The tests were performed by irradiating with γ-rays ( 60Co source) and 10 MeV 11B ions in active (during programming/erase and read-out) and passive (no bias) modes. Comprehensive statistics were obtained by using large memory arrays and comparison of the data with the parameters of irradiated single cells allowed deep understanding of the physical phenomena in the irradiated NROM devices for both moderate (<;1 Mrad) and large (> 1 Mrad) TID. The obtained data is currently employed in the design of the new generation of NROM memories, having improved radiation tolerance.

Structure of the oxide damage under progressive breakdown

Abstract The I–V characteristics of ultra-thin gate oxides under progressive breakdown (BD) show a common behavior, indicative of well-defined general physical features of the BD spot. Transmission electron microscopy (TEM) observations give some hints about this structure and on this basis we propose a physical model of the post-BD current, which is in good agreement with data.

Physical mechanism of progressive breakdown in gate oxides

The definition of the basic physical mechanisms of the dielectric breakdown (BD) phenomenon is still an open area of research. In particular, in advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field; this is of enormous technological importance, and thus widely investigated but still not well understood. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. In this paper, we report for the first time experimental data and a model which provide understanding of the main physical mechanism responsible for the progressive BD growth. We demonstrate the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the ga...

Structure and Conductance of the Breakdown Spot During the Early Stages of Progressive Breakdown

It has been shown that under accelerated stress below ap4 V, thin gate oxides are subject to progressive breakdown (BD), i.e., a gradual growth of the BD spot up to a destructive BD. This paper investigates the conduction mechanisms of the BD spot during the early stages of progressive BD through the measurement of the I-V characteristics using carrier separation. It is shown that a model with no free parameter based on the concept of cotunneling provides a good evaluation of the post-BD current. This model implies a physical microstructure, and its plausibility is compared to direct transmission electron microscopy (TEM) observations

Ionizing Radiation Effects on Non Volatile Read Only Memory Cells

Threshold voltage (<i>V</i>_th) and drain-source current (<i>I</i>_DS) behaviour of nitride read only memories (NROM) were studied both in situ during irradiation or after irradiation with photons and ions. <i>V</i>_th loss fluctuations are well explained by the same Weibull statistics regardless of the irradiation species and total dose. Results of drain current measurements in-situ during irradiation with photons and ions reveal a step-like increase of <i>I</i>_DS with the total irradiation dose. A brief physical explanation is also provided.

Hf-based high-k dielectrics for p-Ge MOS gate stacks

The physical and electrical properties of the gate stack high-k/Al2O3/GeO2/p-Ge were studied in detail, where the high-k is either HfO2 or alloyed HfO2 (HfZrOy, HfGdOx, or HfAlOx). Electrical measurements combined with x-ray photoelectron spectroscopy chemical bonding analysis and band alignment determination were conducted in order to assess the suitability of hafnium-based high-k for this kind of gate stacks, with emphasis on low density of interface states and border traps. HfAlOx was found to be the most promising high-k from those studied. The authors have also found that the current- voltage trends for the various systems studied can be explained by the band alignment of the samples obtained by our x-ray photoelectron spectroscopy analysis.

Comparison of the degradation characteristics of AlON/InGaAs and Al2O3/InGaAs stacks

In this paper, the degradation characteristics of MOS (Metal-Oxide-Semiconductor) stacks with Al2O3/AlON or Al2O3 only as dielectric layers on InGaAs were studied. The dielectric nitrides are proposed as possible passivation layers to prevent InGaAs oxidation. At negative bias, it has been found out that the main contribution to the overall degradation of the gate oxide is dominated by the generation of positive charge in the gate oxide. This effect is pronounced in MOS stacks with Al2O3/AlON as dielectric, where we think the positive charge is mainly generated in the AlON interlayer. At positive bias, the degradation is dominated by buildup of negative charge due to electron trapping in pre-existing or stress-induced traps. For stress biases where the leakage currents are low, the changes in the electrical characteristics are dominated by electron-trapping into traps located in energy levels in the upper part of the semiconductor gap. For stress biases with higher leakage current levels, the electron tra...

Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.