Fernando L. Aguirre

Comparative study of the breakdown transients of thin Al2O3 and HfO2 films in MIM structures and their connection with the thermal properties of materials

In this work, the breakdown transients of A l 2 O 3- and HfO2-based metal-insulator-metal (MIM) stacks with the same oxide thickness and identical metal electrodes were compared. Their connection with the thermal properties of the materials was investigated using alternative experimental setups. The differences and similarities between these transients in the fast and progressive breakdown regimes were assessed. According to the obtained results, A l 2 O 3 exhibits longer breakdown transients than HfO2 and requires a higher voltage to initiate a very fast current runaway across the dielectric film. This distinctive behavior is ascribed to the higher thermal conductivity of A l 2 O 3. Overall results link the breakdown process to the thermal properties of the oxides under test rather than to dissipation effects occurring at the metal electrodes.

Effect of forming gas annealing on the degradation properties of Ge-based MOS stacks

The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge–III-V hybrid devices.The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge–III-V hybrid devices.

Automatic ASET sensitivity evaluation of a custom-designed 180nm CMOS technology operational amplifier

This work presents a SPICE-based automatic SET sensitivity evaluation of a 180nm CMOS full-custom Operational Amplifier. The set-up uses the well known double exponential current law to inject SET into every sensitive node in the circuit hierarchy. The pulse parameters are obtained according to a previously generated population of particles with randomly assigned energies and species, the node bias condition at the instant of the strike and an empirical model obtained through TCAD simulations. The circuit is evaluated transistor-wise for each ion of the generated database and the output waveforms are processed in time and frequency domain to obtain figures of merit of the hardness of the proposed design on a given radioactive environment. Results allow to identify the most sensitive devices and the expected error rate for the projected application, allowing to conduct hardening techniques during early design stages.

Charge trapping effects on Metal-Gate/High-k/III-V MOS devices assessed through C-V hysteresis

In this work, the differences in the trap-ping/detrapping characteristics of Metal-Gate/High-k/III-V MOS stacks is experimentally studied by means of the C-V Hysteresis and dynamic stress. Samples under study include the combination of n-InP and n-InGaAs substrates with HfO2 or Al2O3 dielectrics as gate oxides. This allows to assess the impact of both the substrate and the dielectric on the quality of the complete structure. Results show that Al2O3-based stacks exhibit lower overall trapped charge during hysteresis cycles than their HfO2 counterparts. Additionally, InP-based samples introduce a larger amount of defects above the fermi-level when compared to InGaAs samples for positive stress, but with negligible trapping effects when stressing towards inversion, which is a positive indicator in terms of reliability.

Analysis and comparison of the CV-Dispersion of high-k, bi-layered MOS InGaAs/InP stacks

In this work, the origin of the C-V dispersion in accumulation on High-k Bi-layered InGaAs and InP substrate MOS capacitors is discussed. Using different proportions of Al2O3 and HfO2 dielectrics on a 10nm thick gate insulator, the influence of each layer and its defects is studied. Results show that increasing the thickness of the Al2O3 interfacial layer contributes to improve the quality of the structure in terms of border trap density. InP based stacks show the same tendencies of InGaAs based stacks, but with a higher overall dispersion attributed to the quality of the dielectric deposition on different substrates.

A State-Variable filter as a case study of the Transient Response Analysis Method

In this work the capability of TRAM (Transient Response Analysis Method) for detecting out-of-specification circuits is evaluated. With this purpose we adopt a behavioral point of view, defining a fault as the non compliment of any of the specifications. Although this approach has been previously addressed by many authors, this paper focuses on the usage of more precise simulation models to avoid assumptions of ideal behaviors. We have adopted for the assessment of this method a second order active filter of the State-Variable, implemented in a 180 nm CMOS commercial process with full-custom techniques. Also a methodology that injects random deviations in the circuit components has been considered for creating faulty and non-faulty circuits that will undergo the test.