Ferdinand Gramsamer

Design issues in next-generation merchant switch fabrics

Packet-switch fabrics with widely varying characteristics are currently deployed in the domains of both communications and computer interconnection networks. For economical reasons, it would be highly desirable that a single switch fabric could accommodate the needs of a variety of heterogeneous services and applications from both domains. In this paper, we consider the current requirements, technological trends, and their implications on the design of an ASIC chipset for a merchant switch fabric. We then identify the architecture upon which such a suitable and generic switch fabric could be based, and we present the general characteristics of an implementation of this switching fabric within the bounds of current state-of-the-art technology. To our knowledge, this is the first attempt to design a chipset that can be used for both communications and computer interconnection networks.

Flow control scheduling

Abstract We address a problem associated with credit flow control (FC) schemes for buffered switches, namely, the issue of FC bandwidth and FC optimization, i.e. how many and which credits to return per packet cycle. Using simulations, we show that, under the assumption of bursty traffic with uniform or nonuniform destinations, the number of credits to be returned can be reduced to one, independent of switch size and without loss in performance. Moreover, we introduce the concepts of credit contention and credit scheduling. We analyze five credit-scheduling strategies for a range of system and traffic parameters. Our results demonstrate that with a proper credit scheduler the average packet delay is much lower than with conventional schemes.

Stability of CIOQ switches with finite buffers and non-negligible round-trip time

We propose a systematic method to determine the lower bound for internal buffering of practical CIOQ (combined input-output queued) switching systems. We introduce a deterministic traffic scenario that stresses the global stability of finite output queues. We demonstrate its usefulness by dimensioning the buffer capacity of the CIOQ under such traffic patterns. Compliance with this property maximizes the performance achievable with finite buffers.

Stability degree of switches with finite buffers and non-negligible round-trip time☆

Abstract We answer the question on how much memory a packet switch/router needs; more specifically, we propose a systematic method that is simple, rigorous and general for determining the absolute lower bound of packet buffering required by practical switching systems. Accordingly, we introduce a deterministic traffic scenario that stresses the global stability property of finite output queues and demonstrate its usefulness by dimensioning the internal buffer capacity of two popular CIOQ switches.

Optimizing flow control for buffered switches

We address a problem often neglected in the presentation of credit flow control (FC) schemes for buffered switches, namely the issue of FC bandwidth and FC optimization, i.e. how many and which credits to return per packet cycle. Under the assumption of bursty traffic with uniform destinations, we show via simulations that, independent of switch size and without loss in performance, the number of credits to be returned can be reduced to one. We further introduce the notion of credit contention and credit scheduling. We analyze four credit scheduling strategies under varying system and buffer size. Our results demonstrate that, with a proper credit scheduler in place, contention resolution is resolved much faster than with conventional schemes. Our findings suggest that scheduling of credits is a means for the switch to determine its future arrivals during contention phases.