Ferenc Kovács

An efficient adiabatic charge-recovery logic

We propose a novel dual-rail energy efficient adiabatic charge recovery logic. We completely eliminate nonadiabatic loss during the charge phase, but allow partial reversibility only at nodes with small capacitance, in order to keep the reversibility overhead low. We apply transistor size optimization for a given frequency to alleviate the problem of increasing energy loss at higher operating frequencies. In the case of the nodes with high capacitance, a recovery path is introduced to provide complete charge recovery. The simulation on test circuits with the threshold voltage of 0.8 V showed 34% power reduction on average with complete recovery over the already optimally sized circuit.

A New Web/Matlab Based System in Control Education

Abstract At the Department of Automation, Technical University of Budapest in the last years the basic course of control theory has been renewed significantly using CAD devices, especially Matlab in the computer classroom. In this way the theoretical knowledge became more understandable and convincing for the students. Recently the Internet culture has burst into our everyday life, providing new possibilities for control education, too. It was a challenge lo combine the facilities provided both by the Web and Matlab. In the background of the system the Matlab program package supports the teaching process executing the computations. A new control curriculum using these facilities has been being developed.

Asynchronous Distributed Broadcasting in Cluster Environment

Improving communication performance is an important issue in cluster systems. This paper investigates the possibility of accelerating group communication at the level of message passing libraries. A new algorithm for implementing the broadcast communication primitive will be introduced. It enhances the performance of fully-switched cluster systems by using message decomposition and asynchronous communication. The new algorithm shows the dynamism and the portability of the software solutions, while it has a constant asymptotic time complexity achieved only with hardware support before. Test measurements show that the algorithm really has a constant time complexity, and in certain cases it can outperform the widely used binary tree approach by 100 percent. The presented algorithm can be used to increase the performance of broadcasting, and can also indirectly speed up various group communication primitives used in standard message passing libraries.

A new, phonocardiography-based telemetric fetal home monitoring system.

The purpose of this article is to describe a new, phonocardiography-based fetal telemonitoring system, which, due to its passive nature, allows long-term measurements even at the home of the pregnant woman. The input element of the system was the home monitor with two sensors for recording the trans-abdominal fetal heart signal and the uterine contractions. The recorded signal was transmitted by mobile network and Internet to an Evaluation Center, where it was analyzed in detail to obtain information about possible dysfunction of the fetal heart. The investigations on this system made clear that by advanced processing of the recorded signal the system captured many additional cardiac features compared with the traditional ultrasound-based cardiotocographic procedure.

A proposed synthesis method for Application-Specific Instruction Set Processors

Due to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.

Utilising Internet in Teaching Control Theory

Abstract This paper is about problems of realization of teaching control theory interactively. We introduce a new interactive, World Wide Web based teaching model and an implementation in control theory. What makes this model new is that on the client- side you only need a Web browser and you are also able to interactively practice sophisticated, topic-related exercises.

Two-level Pipeline Scheduling of Adiabatic Logic

We present an integer linear programming (ILP) formulation and a heuristic scheduling approach for high-level synthesis to synthesize two-level pipeline datapaths using four-phase adiabatic logic. Adiabatic CMOS logic that relies on charge recovery is attractive to achieve low energy dissipation. It complements voltage-scaling approaches, while its inherent pipeline structure makes it most suitable for signal processing applications. However, the differences between adiabatic and static logic, such as the phase clock controlled evaluation of each logic stage influences the automated design tools, making existing scheduling algorithms unsuitable for adiabatic circuits. We also present a VHDL description technique to perform functional simulation of the synthesized adiabatic datapath together with the static part of a digital system, and provide experiments to show the viability of our approach.

Performance prediction for association rule mining algorithms

Execution time prediction is very important issue in job scheduling and resource allocation. Association rule mining algorithms are complex and their execution time depends on both the properties of the input data sources and on the mining parameters. In this paper, an analytical model of the Apriori algorithm is introduced, which is based on statistical parameters of the input dataset (average size of the transactions, number of transactions in the dataset) and on the minimum support threshold. The developed analytical model has only few parameters therefore the predicted execution time can be calculated in a simple way. The investigated domain of the input parameters covers the most commonly used datasets, therefore the introduced model can be used widely in field of association rule mining. The constant parameters of the model can be identified in small number of test executions. The developed model allows predicting the execution time of the Apriori algorithm in a wide range of parameters. The suggested model was validated by several different datasets and the experimental results show that the overall average error rate of the model is less than 15%

Design procedure based on VHDL language transformations

Automated hardware synthesis starting from the register transfer level (RT-level) VHDL description is well established. However, starting the design on a higher abstraction level than the RT-level is one of the major problems within the VHDL based system synthesis. We present a novel design procedure called SYLANT (Synthesis based on Language Transformations), which uses the methodology of high-level synthesis. It starts from the abstract functional model and produces an RT-level description through successive language transformations. The biggest advantage of this method is that no other description technique than the standard VHDL is considered. The intermediate VHDL code is accessible to the designer, the circuit model can be simulated after each design step. Different algorithms can be implemented for any step, depending on the applied technology dependent information and various RT-level architectures can be obtained. The output VHDL format is suitable to continue the design flow with RT-level based synthesis tools.

A proposed method for dynamic fitting of MOS model parameters

A method for optimization of MOS model parameters is introduced. The method is based upon dynamically fitting the measured frequency response of a reconfigurable ring oscillator. The ring oscillator contains two added switching transistors and two loading capacitors. By controlling the switching transistors, the capacitive load of the inverters and thus the oscillation frequency can be varied. The simulated and the measured frequencies are compared and the derived average error is minimized. Sequential iterations using combined mathematical methods are applied to the procedure. Simplifications are introduced in order to shorten the computational time. The effectiveness of the method on improving the accuracy of simulation is demonstrated with numerical examples. >