Fermín Sánchez

Guidelines for the final year project assessment in engineering

This paper presents an efficient and objective procedure for the outcome-based assessment of engineering final year projects (FYP). The procedure, consisting of 6 steps, can easily be customized for different engineering curricula. A User Guide has been developed to help institutions create their own FYP assessment system. The guide includes the assessment procedure and aids for its implementation. Particularly, a set of FYP-oriented observable descriptors for Tuning outcomes was defined. The end-products of the proposed assessment procedure are a set of assessment reports that the evaluator agent/s must fulfil per milestone, marking the level reached by the student at every descriptor (0: unacceptable, 1: minimum acceptable, 2: good, 3: excellent). These marks are then gathered together in an overall assessment sheet showing, for every learning outcome, the evolution along the assessment milestones of the level reached by the student at any descriptor. This sheet is a very powerful tool for setting the final mark. All assessment agents use the same list of descriptors and the same levels of acquisition, thus improving the consistency, traceability and global quality of the assessment process.

Time-constrained loop pipelining

This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on dividing the problem into two simpler and independent tasks: retiming and scheduling. TCLP explores different sets of resources, searching for a maximum resource utilization. This reduces area requirements. After a minimum set of resources has been found, the execution throughput is increased and the number of registers required by the loop schedule is reduced. TCLP attempts to generate a schedule which minimizes cost in time and area (resources and registers). The results show that TCLP obtains optimal schedules in most cases.

A methodology to introduce sustainability into the final year project to foster sustainable engineering projects

The introduction of sustainability skills into higher education curricula is a natural effect of the increasing importance of sustainability in our daily lives. Topics like green computing, sustainable design or environmental engineering have become part of the knowledge required by todays engineers. Furthermore, we strongly believe that the introduction of this skill will eventually enable future engineers to develop sustainable products, services and projects. The Final Year Project is the last academic stage facing students and a step towards their future professional engineering projects. As such, it constitutes a rehearsal for their professional future and an ideal opportunity for reflecting on whether their Final Year Project is sustainable or not, and to what extent. It also provides a good tool for reviewing the lessons learned about sustainability during the degree course and for applying them in a holistic and integrated way. In this paper, we present a guide that allows both students and advisors to think carefully about the sustainability of engineering projects, in particular the Final Year Project.

Cluster-level simultaneous multithreading for VLIW processors

Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. However, while some applications exhibit large amounts of instruction level parallelism (ILP) and benefit from very wide machines, others have little ILP, which wastes precious resources in wide processors. Simultaneous multithreading (SMT) is a well known technique that improves resource utilization by exploiting thread level parallelism at the instruction grain level. However, implementing SMT for VLIWs requires complex structures. In this paper, we propose CSMT (cluster-level simultaneous multithreading) to allow some degree of SMT in clustered VLIW processors with minimal hardware cost and complexity. CSMT considers the set of operations that execute simultaneously in a given cluster (named bundle) as the assignment unit. All bundles belonging to a VLIW instruction from a given thread are issued simultaneously. To minimize cluster conflicts between threads, a very simple hardware- based cluster renaming mechanism is proposed. The experimental results show that CSMT significantly improves ILP when compared with other multithreading approaches suited for VLIW. For instance, with 4 threads CSMT shows an average speedup of 113% over a single-thread VLIW architecture and 36% over interleaved multithreading (IMT). In some cases, speedup can be as high as 228% over single thread architecture and 97% over IMT.

Merge Logic for Clustered Multithreaded VLIW Processors

Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. Simultaneous MultiThreading (SMT) is a well known technique that uses thread level parallelism at the instruction grain level. However, implementing SMT for VLIW requires complex structures. CSMT (cluster-level simultaneous MultiThreading) allows some degree of SMT in clustered VLIW processors with minimal hardware cost and complexity. This paper deals with the hardware required to implement CSMT instruction merge logic on a clustered VLIW processor. The paper presents two implementations of CSMT merge logic and an analysis of both comparing design issues like delay and number of transistors required.

CSMT: Simultaneous Multithreading for Clustered VLIW Processors

Simultaneous MultiThreading (SMT) is a well-known technique that improves resource utilization by exploiting thread-level parallelism at the instruction grain level. However, implementing SMT for VLIWs requires complex structures, which is contrary to the VLIW philosophy of hardware simplicity. In this paper, we propose Cluster-level Simultaneous MultiThreading (CSMT) to allow some degree of SMT in clustered VLIW processors with low hardware cost and complexity. CSMT considers the set of operations that execute simultaneously in a given cluster as the assignment unit. To minimize cluster conflicts between threads, a very simple hardware-based cluster renaming mechanism is proposed. The hardware required to implement CSMT is cheap, realistic, and practical for a clustered VLIW processor. An analysis of the hardware required to implement CSMT shows that it is quite scalable, with up to eight threads easily supported at low hardware cost. The experimental results show that CSMT significantly improves performance when compared with other multithreading approaches suited for VLIW. For instance, with four threads, CSMT shows an average speedup of 110 percent over a single-thread VLIW architecture and 40 percent over Interleaved MultiThreading (IMT). In some cases, speedup can be as high as 225 percent over single-thread architecture and 84 percent over IMT.

Resource-constrained pipelining based on loop transformations

Abstract In this paper a novel technique for resource-constrained loop pipelining is presented. RCLP is based on several dependence graph operations: loop unrolling, operation retiming, resource-constrained scheduling, and span reduction. All these operations are focused to find a minimum length aschedule able to be executed with a limited number of resources and thus maximizing resource utilization. The results obtained show that RCLP is superior to the existing software-pipelining-based approaches. This technique has also been evaluated with 300 randomly generated loop dependence graphs. In all cases a time-optimal schedule has been found.

A take-home exam to assess professional skills

Professional Skills, such as the ability to communicate effectively or the ability to gather and integrate information, are not easy to teach or to assess. A traditional exam is not the best way of assessing these skills because it is limited both by time and by the resources students are able to consult. Moreover, in a traditional exam it is difficult to assess if professional skills have been acquired in depth. In this paper we propose to substitute the traditional exam by a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. We also analyze what kind of questions should be asked to evaluate professional skills, as well as analyzing the potential drawbacks of these kind of exams (such as inappropriate student behavior). Finally, we show the results of one subject at the Barcelona School of Informatics, in which the take-home exam replaced the traditional exam. This course has been taught over 11 terms with good results.

RESIS: A New Methodology for Register Optimization in Software Pipelining

This paper presents a new technique to reduce the register pressure in pipelined schedules. A two-step approach is proposed: minimizing the SPAN of the loop and rearranging operations within a basic block. Experimental results show that further improvements on the schedules found by the best existing techniques can be obtained at the expense of a negligible computational cost.

Evaluation and assessment of professional skills in the Final Year Project

In this paper, we present a methodology for Final Year Project (FYP) monitoring and assessment that considers the inclusion of the professional skills required in the particular engineering degree. This proper monitoring and clear evaluation framework provides the student with valuable support for the project implementation as well as for improving the quality of the projects, thereby reducing the academic drop-out rate. The proposed methodology has been implemented at the Barcelona School of Informatics at the Universität Politècnica de Catalunya - BarcelonaTech. The FYP is structured around three milestones: project definition, project monitoring and project completion. Skills are assigned to each milestone according to the tasks required in that phase, and a list of indicators is defined for each phase. The evaluation criteria for each indicator at each phase are specified in a rubric, and are made public both to students and teachers. Thus, the FYP includes an exhaustive evaluation method distributed throughout the whole project implementation, thereby facilitating project organization for the student as well as providing a clear and homogeneous assessment framework. The methodology for the FYP organization, assessment and evaluation was launched and piloted over two semesters. We believe the experience to be general in the sense that it has been conducted as part of an ICT engineering degree, but may easily be extended to any other engineering degree.