Fernando Antonio Pinto Barúqui

Linearly Tunable CMOS OTA With Constant Dynamic Range Using Source-Degenerated Current Mirrors

This brief introduces a new operational transconductance amplifier (OTA) that maintains the input voltage-swing constant during gm adjustments, enabled by employing current mirrors with source degeneration. The OTA presents a wide gm tuning range, which is linearly accomplished through a variable current source. The key design steps are illustrated through an example, and simulation results are included to validate the theory

A 48-16-MHz CMOS SC decimation filter

This paper presents a CMOS switched-capacitor decimation filter for prefiltering operations in video communications systems, reducing the complexity of continuous-time antialiasing filters and alleviating dynamic range requirements of analog-to-digital converters. As a consequence of the structures low sensitivity to process variations, predicted by theory and verified in the laboratory by measurements on all samples of the same batch, it was possible to apply capacitor arrays having minimum feasible size units of 100 fF to implement the filter coefficients, leading to substantial savings in power consumption. Implemented in a standard 0.8-/spl mu/m CMOS process with poly-poly capacitors, the experimental device samples the incoming continuous-time analog signal at 48 MHz and presents a filtered sampled-data output at 16 MHz, with a measured pass-band deviation smaller than 0.22 dB up to the cutoff frequency of 3.6 MHz, output noise power spectrum of 1.1 nV/sub RMS///spl radic/(Hz) and a signal handling ability of 1.4 V/sub pp/, resulting in a dynamic range of 48 dB, meeting the usual specifications for video-frequency signal processing.

Recursive switched-capacitor Hilbert transformers

Efficient implementation of discrete-time Hilbert transformers using switched-capacitor techniques is presented. The proposed network is composed of structurally allpass filters as basic building blocks. As a result, the phase difference of 90 degrees is obtained, for the Hilbert transform pair, with very small sensitivity with respect to capacitance ratio errors. A design example is considered, which includes experimental results obtained in the laboratory with a prototype Hilbert transformer.

Tunable analog loudspeaker crossover network

This paper proposes a new implementation of tunable analog loudspeaker crossover networks suitable to monolithic integrated circuit (IC) realizations. The crossover frequency is linearly set by tuning voltages to adequate the audio reproduction to different environments and loudspeaker characteristics over the entire audio spectrum. Based on structurally allpass networks, the proposed approach presents very low sensitivity to IC device mismatching. This is verified by simulation and comparison with an alternative design. Details of the tuning procedure are provided. Experimental verification of the structure low sensitivity and tuning capabilities is also shown.

Direct-form SC filters with low frequency response sensitivity to the transfer function coefficients

The inclusion of mutually canceling pole-zero pairs in transfer functions having denominator order smaller than numerator order, to achieve low sensitivity of IIR direct-form SC filters to coefficient variations, is studied. Comparisons with the conventional elliptic SC filter design are shown to verify the effectiveness of the proposed approach. Monte Carlo analysis and Spice simulations carried out on a prototype filter designed in a 0.35-mum CMOS technology are presented to validate the theory.

Bulk-tuned Gm-C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom?s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35µm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.

IC design of an analog tunable crossover network

This paper presents a tunable crossover circuit for audio applications, to be implemented in a standard 0.35 /spl mu/m CMOS process. The circuit is based on the decomposition of low-pass and high-pass transfer functions into two structurally all-pass building blocks. The transconductors (OTA) incorporate source degenerated current mirrors (SDCM), to allow wide and highly linear tuning range, while keeping the input and output signal swings constant. Simulation results, with practical process parameters, are presented.

A recursive switched-capacitor decimation filter design for 0.8 /spl mu/m CMOS technology

This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5.5 V for a 0.8 /spl mu/m technology. Also shown are electrical simulations using PSPICE 5.0 considering both typical and worst case conditions for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The filter dissipates approximately 46 mW (including the output buffer) at 5.5 V, and presents a flat frequency response within 0.12 dB from dc to 3.56 MHz.

Very-low-tranconductance CMOS amplifier using multi-tanh bulk-driven input stage with gate-controlled assymetry for G m -C applications

A novel structure of the multi-tanh bulk-driven input stage OTA is presented in this paper. The circuit was designed and simulated in a 130nm CMOS process. The results show a nominal transconductance of 1.593 nS with an input linear range of 400 mVpp, assuming a THD no greater than -40 dB. The system supply voltage is 1.2 V (given by the technology), and the power consumption goes up to 315.7 nW. The achieved ultra low transconductance, along with the wide linear range (33% of the dynamic range) makes the transconductor highly suitable for low-frequency biomedical Gm-C applications. Furthermore, Monte Carlo analysis was conducted and showed the circuit possesses high resilience to process variation and mismatch: transconductances standard deviation lower than 4% of its nominal value, and maximum THD of -40 dB.

Focal-plane image encoder with cascode current mirrors and increased vector quantization bit rate

Focal-plane processing is the target of many studies due to its potential for enhancing the speed of the vision system flow. With focal-plane processing it is possible to perform parallel processing throughout the entire matrix. Usually, in vision systems, analog-to-digital conversion (ADC), transmission and storage represent a bottleneck. In order to alleviate these constraints, analog image compression is implemented at the focalplane, thereby reducing the amount of data to be transmitted and the bandwidth requirements. The ADC is performed at the focal-plane as well, after the compression operation whose realization is based on differential pulse-code modulation (DPCM), linear transform and vector quantization (VQ) applied on every 4 × 4 pixel block using current-mode circuits. This paper presents experimental results obtained from the second-generation of an image sensor. The main contributions in comparison to the previous realization are: increase of the vector quantizer complexity, number of bits per pixel, pixel matrix size, and the use of cascode current mirrors in the linear transform matrix. The image sensor advanced in this paper was fabricated in a standard 180 nm CMOS process.