Carlos Fernando Teodósio Soares

Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization

In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching.

A low-transconductance OTA with improved linearity suitable for low-frequency Gm-C filters

A fully differential operational transconductance amplifier is presented in this paper with enhanced linearity and low transconductance, suitable for low-frequency Gm-C filters. This paper also proposes a new common-mode feedback scheme that presents low sensitivity to large differential voltage swings at the OTA outputs. The proposed OTA was employed in the design of a fully-integrated Gm-C low-pass filter with a cutoff frequency of 30kHz. The Gm-C filter was fabricated in a 0.35µm CMOS technology and presented a THD at the output less than 1% for input signals with differential amplitudes up to 3.2V.

Automatic placement of identical unit capacitors to improve capacitance matching

Capacitance matching is a critical issue in several analog and mixed-signal designs such as switched-capacitor filters, A/D and D/A converters. Using identical unit capacitors in parallel to implement each capacitor in the design, combined with a careful layout, is the best technique to achieve a good capacitance matching. Common-centroid geometry is the most widely used layout technique for matching capacitors, because this placement improves the immunity against process gradients. However, the common-centroid geometry is not the only possible placement that has this feature. In this paper, other possible placements, which are also immune to process gradients, are presented. These alternative geometries are specially suitable for layouts where the number of unit capacitors do not allow a perfect common-centroid placement. Since finding these alternative layouts is a very difficult task, this paper proposes an automated method to find the optimal placement for an array of unit capacitors.

Optimizing Capacitance Ratio Assignment for Low-Sensitivity SC Filter Implementation

Accurate capacitance matching is essential for switched-capacitor filters implementation because the filter coefficients depend upon the capacitance ratios. The use of identical unit capacitors in parallel to form larger capacitances and careful layout design can provide, in many cases, an accuracy of 0.1%. Unfortunately, this technique can be directly applied only if the filter coefficients are rational numbers. In general, coefficient approximations are required, leading to frequency response errors. In this paper, a new design method, using a genetic algorithm, is proposed to find the optimum capacitance ratio approximations by rational numbers which minimize the total number of unit capacitors for a given acceptable frequency response error, in order to save die area.

Phase Locked Loop for automatic tuning of low-frequency Gm-C filters

Transfer functions implemented by Gm-C filters depend on absolute values of transconductance and capacitances, which are greatly affected by variations in the fabrication process. Hence, a design procedure that makes the filter cutoff frequency precisely defined, despite the influences of fabrication process variations is necessary. This work develops a Phase-Locked Loop (PLL) in order to detect such variations and enable the automatic adjustment of a Gm-C filter cutoff frequency. An important aspect of the proposed approach is the design of an operational transconductance amplifier (OTA) that presents a highly linear behavior in a wide range of input differential voltages. Spice simulations, including Monte Carlo analysis, using BSIM3v3 device models of a 0.35 µm CMOS technology were performed to verify the robustness of the proposed design approach.

Capacitance ratio approximation in SC filters via genetic algorithm

Accurate capacitance matching is a critical issue for switched-capacitor (SC) Alter implementations. Using identical unit capacitors in parallel to form larger capacitances and careful layout design can provide an accuracy of 0.1%. However, this technique can be directly applied only if the Alter coefficients are rational numbers. In general, coefficient approximations are required, leading to frequency response errors. In this paper, a new design method, using a genetic algorithm (GA), is proposed to and the optimum capacitance ratio approximations by rational numbers that produce acceptable frequency response errors and minimize the total number of unit capacitors in order to save die area. Design examples in 0.35 mum CMOS are presented and simulated to illustrate the proposed method.

A constrained optimization approach for accurate and area efficient bandgap reference design

In this paper, a constrained optimization approach for the design of bandgap reference (BGR) circuits that meet a given voltage inaccuracy specification while minimizing area is presented. Device matching properties and error propagation analysis are carried out such that the desired performance can be achieved by the optimization algorithm. The BGR occupies 0.097mm2 in a 0.35m CMOS process. Experimental results verified the effectiveness of the optimization algorithm by producing a voltage reference of 1.220V, with a relative inaccuracy (3/) of 0.65% at 27C and TC=13.7ppm/C in the range of 10C to 125C, for all 40 fabricated samples, without trimming. Also shown in the paper and verified experimentally, a 3-fold reduction in inaccuracy, to 0.20% at 27C, can further be obtained, if needed, by a simple one-temperature four-bit trimming.

A systematic method to approximate capacitance ratios to improve capacitance matching in SC filters

A critical issue in the design of switched-capacitor (SC) filters is the capacitance matching, because the filter coefficients depend on capacitance relative values - capacitance ratios. The most successful design method to achieve an accurate capacitance matching employs a parallel arrangement of identical unit capacitors to implement each filter capacitor. This method, combined with a careful layout design, can achieve a capacitance matching accuracy of 0.1%. However, the procedure can be directly applied only if the filter coefficients can be written as rational numbers, since each capacitor is implemented as an integer number of capacitors in parallel. This paper presents a systematic procedure, with low computational effort, to approximate the filter coefficients by integer ratios without causing significant errors in the filter frequency response, whereas keeping the total number of unit capacitors small, in order to save die area. This procedure is applied in a design example of a SC band-pass filter, which has been fabricated in a 0.35 mm CMOS technology.