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A DSP based IP set-top box for home entertainment

In this paper, the implementation of a digital signal processor (DSP) based Internet protocol set-top box for home entertainment networks is described. The main functional blocks are the MPEG-2 transport stream demultiplexer, the audio and video decoders and the audio and video display management modules (with on-screen display capabilities). All blocks have been built into a single low-cost DSP to allow multi-format operation in the future. A prototype has been designed and fully tested in a real environment. Currently the set-top box works with a fully optimized MPEG-2 video decoder. A preliminary version of an MPEG-4 video decoder is available now and we are also working in an MPEG-4/AVC (H.264) decoder

A DSP Based H.264 Dec oder for a Multi-Format IP Set-Top Box

In this paper, the implementation of a digital signal processor (DSP) based H.264 decoder for a multi-format set-top box is described. Baseline and main profiles are supported. Using several software optimization techniques, the decoder has been fitted into a low-cost DSP. The decoder alone has been tested in simulation, achieving real-time performance with a 600 MHz system clock. Moreover, it has been integrated in a multi-format IP set-top box allowing the implementation of actual environment tests with excellent results. Finally, the decoder has been ported to a latest generation DSP.

An H.264 video decoder based on a latest generation DSP

Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor have been fully exploited to increase the execution speed. Profiling tests have been carried out by using digital TV streams and DVD transcoded sequences. The speed of the new DSP running the decoder is 16% better than that of a forerunner with 20% more internal memory running the same decoder.

Complexity analysis of an HEVC decoder based on a digital signal processor

High Efficiency Video Coding (HEVC) is a new video coding standard created by the JCT-VC group within ISO/IEC and ITU-T. HEVC is targeted to provide the same quality as H.264 at about half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. Up to now, only a few decoder implementations have been reported, most of them oriented to carry out a complexity analysis. In this paper, a DSP-based implementation of the HEVC HM9.0 decoder is presented. Up to the best of our knowledge, it is the first DSP-based implementation shown in the scientific literature. Several tests have been carried out to measure the decoder performance and the computational load distribution among its functional blocks. These results have been compared with the ones obtained with the decoder implementations reported up to date. Finally, based on the results obtained in previous works regarding software optimization of DSP-based decoders, realtime could be achieved for SD formats with a single DSP after optimizing our HEVC decoder. For HD formats, multi-DSP technology will be needed.

A DSP-Based HEVC decoder implementation using an actor language dataflow model

During the last decades, new video compression standards arose every few years with always higher compression gains and considerable increases on the computational cost. Single core processors have reached their limit and multicore processors are there to overcome this issue to give more processing power. In order to accelerate the implementation of new video coding standards, MPEG has standardized an alternative framework to describe video decoders. It is based on reference decoders written in the RVC CAL dataflow actor language. From these descriptions, a compiler - Open RVC CAL compiler (Orcc) - allows the automatic generation of C code dedicated to the target processor. In this paper, a DSP based decoder compliant with the new High Efficiency Video Coding (HEVC) standard has been implemented using a CAL RVC model as a starting point. This is the first implementation of an HEVC decoder with DSP technology based on a HEVC RVC CAL model. The decoder has been compared in performance with a GPP implementation, also based on the RVC CAL model, and outperforms it by more than 50%. Additionally, the performance of this decoder is compared with that of other DSP-based HEVC decoders implemented without using the Orcc infrastructure1.

Maximizing the user experience with energy-based fair sharing in battery limited mobile systems

Currently, the usefulness of many mobile systems is largely limited by the battery lifetime. In this paper, energy-based fair queuing (EFQ) is proposed as a pivotal instrument to maximize the user experience in this type of system. Energy-based fair queuing is a novel class of energy-aware scheduling algorithms that support proportional energy use, effective time-constraint compliance and a flexible trade-off between them. The combination of EFQ with lifetime-oriented power management schemes opens the door to maximize the user experience of battery-limited mobile systems. Moreover, it is suggested to merge traditional energy-efficient algorithms with EFQ to further improve the user experience. The proposed EFQ algorithm is implemented in the Linux kernel V3.3 and verified on a testbench based on an open source Linux scheduler simulator with user-specified energy loads. Simulation results show that EFQ is more effective and flexible than the Linux scheduler in maximizing the user experience of energy-limited mobile systems.

A real-time H.264 MP decoder based on a DM642 DSP

In this paper, the implementation of a baseline profile H.264 decoder based on a DM 642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the algorithm have been encoded directly in assembly code to increase the number of instructions per cycle. The decoder has been tested in simulation with actual (transcoded) DVD and digital TV streams. According to these tests, standard definition real time decoding can be obtained with a DM 642@600 MHz.

On an implementation of HEVC video decoders with DSP technology

High Efficiency Video Coder (HEVC) will become a new MPEG International Standard by the end of 2012. HEVC is targeted to provide the same quality as H.264 at about a half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. In this paper, a preliminary implementation of an HEVC video decoder based on a DSP is presented and compared with a formerly developed H.264 DSP-based decoder.

A DSP based H.264/SVC decoder for a multimedia terminal

In this paper, the implementation of a DSP-based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. A PC-based decoder implementation has been ported to a commercial DSP. Performance optimizations have been carried out improving the initial version performance about 40% and reaching real time for CIF sequences. Moreover, the performance has been characterized using H.264/SVC sequences with different kinds of scalabilities and different bitrates. This decoder will be the core of a multimedia terminal that will trade off energy against quality of experience.

An H.264 video decoder based on a DM6437 DSP

In this paper, an H.264 video decoder based on the new TMS320DM6437 (DaVinci) DSP is described. In this work both, DMA and memory architecture of the processor are fully exploited to improve the decoder performance. Profiling tests have been carried out in simulation using digital TV streams and DVD transcoded sequences. Performance is 10% better than that of the same decoder based on a TMS320DM642 DSP.