M. Chavarrias

Complexity analysis of an HEVC decoder based on a digital signal processor

High Efficiency Video Coding (HEVC) is a new video coding standard created by the JCT-VC group within ISO/IEC and ITU-T. HEVC is targeted to provide the same quality as H.264 at about half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. Up to now, only a few decoder implementations have been reported, most of them oriented to carry out a complexity analysis. In this paper, a DSP-based implementation of the HEVC HM9.0 decoder is presented. Up to the best of our knowledge, it is the first DSP-based implementation shown in the scientific literature. Several tests have been carried out to measure the decoder performance and the computational load distribution among its functional blocks. These results have been compared with the ones obtained with the decoder implementations reported up to date. Finally, based on the results obtained in previous works regarding software optimization of DSP-based decoders, realtime could be achieved for SD formats with a single DSP after optimizing our HEVC decoder. For HD formats, multi-DSP technology will be needed.

A DSP-Based HEVC decoder implementation using an actor language dataflow model

During the last decades, new video compression standards arose every few years with always higher compression gains and considerable increases on the computational cost. Single core processors have reached their limit and multicore processors are there to overcome this issue to give more processing power. In order to accelerate the implementation of new video coding standards, MPEG has standardized an alternative framework to describe video decoders. It is based on reference decoders written in the RVC CAL dataflow actor language. From these descriptions, a compiler - Open RVC CAL compiler (Orcc) - allows the automatic generation of C code dedicated to the target processor. In this paper, a DSP based decoder compliant with the new High Efficiency Video Coding (HEVC) standard has been implemented using a CAL RVC model as a starting point. This is the first implementation of an HEVC decoder with DSP technology based on a HEVC RVC CAL model. The decoder has been compared in performance with a GPP implementation, also based on the RVC CAL model, and outperforms it by more than 50%. Additionally, the performance of this decoder is compared with that of other DSP-based HEVC decoders implemented without using the Orcc infrastructure1.

A multicore DSP HEVC decoder using an actorbased dataflow model and OpenMP

Video coding is one of the most demanding applications, in terms of computational cost, for portable multimedia terminals. In the last years, the new video coding standards, like High Efficiency Video Coding (HEVC), and the increasing resolutions of video codecs have overtaken the capacities of the single core processors in embedded systems. In consequence, multicore architectures are used in current multimedia systems. Besides, new methodologies and frameworks are arising to speed-up the design cycle. In this paper, a methodology based on the Reconfigurable Video Coding CAL Actor Language (RVC-CAL) and the OpenMP API has been used to implement an HEVC decoder based on a multicore DSP. A RVC-CAL description of the HEVC decoder has been used as starting point. The Open RVC-CAL compiler framework (Orcc) has been used to generate C-code from the RVC-CAL specification. This code and the OpenMP library have been ported to the multicore DSP environment. Decoders running on 1, 2, 3 and 4 cores have been tested. Also, the multi DSP based HEVC decoder has been compared with other implementations based on multicore GPPs.

An automatic tool for the static distribution of actors in RVC-CAL based multicore designs

The Open RVC CAL compiler infrastructure allows the definition and simulation of complex algorithms as a set of interconnected dataflow actors using the RVC-CAL actor language as well as the automatic generation of C code for a number of target processors, like ARM or x86 based cores. Though code for multicore processors may also be generated, mapping among actors and cores is carried out by hand. With complex algorithms, usually described with tens of actors, this mapping procedure requires expertise and a deep knowledge of the algorithms. In this paper, an automatic tool to assist in the actor-core mapping for multicore systems designed using the Orce infrastructure is presented. The new tool automatically explores all possible mappings by simulation and recommends the most efficient in terms of speed. The tool has been tested with two complex video decoding algorithms (H.264 and HEVC). The tests show that the automatic tool obtains good results compared with those obtained by an expert designer.

Real-time HEVC decoding with OpenHEVC and OpenMP

HEVC codecs will replace H.264 ones inside the consumer electronic devices in the near future. In this work, the open source OpenHEVC decoder has been modified in order to support parallel decoding at the slice level using OpenMP instead of pthreads. The advantage of this unthreaded decoder is that it can be used with any architecture, providing it supports OpenMP. Tests have been carried out with three different multicore chips and the performance results are similar to those obtained with the pthreaded OpenHEVC decoder.

Design of multicore HEVC decoders using actor-based dataflow models and OpenMP

This paper explains the design of a new back-end for the Open Reconfigurable Video Coding CAL Actor Language compiler framework (Orcc). This back-end uses the OpenMP API instead of the pthreads library to automatically generate C code for any multicore architecture with OpenMP support. With this back-end, implementations of an HEVC decoder have been automatically generated and tested for three different multicore target architectures. The new back-end does not introduce a performance penalty regarding to the actual C back-end, and enables the use of new target architectures, such as DSPs.

3D videoconferencing system using spatial scalability

An implementation of a real-time 3D videoconferencing system using the currently available technology is presented. This approach is based on the side by side spatial compression of the stereoscopic images. The encoder and the decoder have been implemented in a standard personal computer and a conventional 3D compatible TV has been used to present the frames. Moreover, the users without 3D technology can use the system because 2D compatibility mode has been implemented in the decoder. The performance results show that a conventional computer can be used for encoding/decoding audio and video streams and the delay in the transmission is lower than 200 ms.

A DSP-based HEVC decoder implementation using RVC-CAL and native OpenHEVC code

Complexity of both, applications and processors, is permanently increasing. While, designers must face with a lot of challenges, such as reduced time to market, performance and energy efficiency, among others. In this context, dataflow based methodologies and tools, like the Open RVC-CAL Compiler Infrastructure (Orcc), have revealed powerful in supporting platform independent design. Within the Orcc design flow, applications are described using the RVC-CAL language. A set of Orcc backends can generate different source codes (e.g., C, C++, VHDL, Java) that must be finally compiled for a target platform with a native compiler. This approach has several advantages, but the quality of the final product is limited by the quality of the currently implemented backends. In this work, an HEVC decoder implementation for DSP technology has been developed by using a combination of RVC-CAL descriptions and native C-code. The results of this approach are compared with those obtained by using both, a pure RVC-CAL description and a pure native C-code implementation.