Fernando Silveira

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

LC-VCO Design Optimization Methodology Based on the

In this paper, an LC voltage-controlled oscillator (LC VCO) design optimization methodology based on the gm/ID tech nique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the com promises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.

g_m/I_D

In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

Ratio for Nanometer CMOS Technologies

A synchronous polarimeter was set up for the measurement of small rotation angles of the polarization plane of light. The polarimeter is based on a polarizer-Faraday modulator-analyzer structure with a synchronous detection scheme, which produces a linear system response. The theoretical background is studied, and the system performance is investigated experimentally. We achieved an accuracy of the order of 10(-4) deg, or 5 mg/dl of glucose in a 1-cm light path.

MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

The design and test of a micropower signal conditioning circuit for a piezoresistive accelerometer is presented. The circuit is intended for sensing human body motion in rate-adaptive cardiac pacemakers. A strategy is proposed to allow handling of the piezoresistive sensor with the desired level of consumption. Experimental results show the fabricated circuit is able to measure accelerations in the range from 0.04 g to 0.34 g with a total consumption of less than 3 /spl mu/A with supply voltages down to 2 V.

Precision synchronous polarimeter with linear response for the measurement of small rotation angles.

This work deals with two aspects of the reuse and redesign of analog circuits. First, a method for technology migration of analog circuits, recently proposed by Galup-Montoro and Schneider (Proc. SBCCI2000, pp. 89-93, 2000), is validated experimentally in the redesign of a Miller OTA from a 2.4 /spl mu/m technology to a 0.8 /spl mu/m technology. In addition, the impact of the method on performance aspects of analog circuits not covered in the original proposal (slew rate and current mirror frequency response) is studied. As a second mechanism for allowing the reuse of analog circuits, the feasibility of the application of the reference bias current as a tuning parameter to customize the performance of an existing design to suit different applications is demonstrated.

Design of a micropower signal conditioning circuit for a piezoresistive acceleration sensor

Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions.

Experiences on analog circuit technology migration and reuse

In this paper Geometric Programming is successfully applied to the power optimization of CMOS operational amplifiers using a model valid in all regions of inversion (weak, moderate and strong), which assures a true globally optimal design. A complete transistor model presents some problems on the formulation of the Geometric Program. We will show in this paper that in the case of power optimization, a careful analysis of the physical meaning of the conflicting model equations, allow us to overcome these problems in a simple and efficient way. The proposed algorithm is tested in several cases for a Miller amplifier, showing how the optimum inversion level spans all the inversion regions as the target bandwidth changes.

MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design

This article presents a design methodology for the most simple cascode transistors bias circuit, i.e. a diode-connected transistor, valid from weak to strong inversion. By taking advantage of a compact MOS transistor model, we show how the circuit can be easily designed to precisely fix the drain voltage of the cascoded transistor just above its saturation voltage. Test circuits were manufactured in a 0.35μm CMOS technology in order to test the design methodology under different operation regions (weak, moderate and strong inversion) and for long and short channel transistors. Standard deviation in measured drain voltage of the cascoded transistor is below 3% of its mean.