Lirida A. B. Naviner

On design and implementation of a decimation filter for multistandard wireless transceivers

In this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed filtering cascade structure. The filter processes six-bit data stream input from a fourth-order sigma-delta modulator and has been prototyped in a field-programmable gate array device.

Design of Down-Sampling Processors for Radio Communications

This paper deals with design and implementation of digital filter processors to be used as down-samplers in wireless transceivers. We consider a homodyne direct conversion and propose an improved method to specify each stage of the cascade structure. The proposed scheme results in a globally compact implementation. The method is detailed for DECT standard and illustrated by a fixed point FPGA based implementation.

Design and hardware implementation of digital channel selection processor for radio receiver

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for radio receiver. For an homodyne wide-band RF receiver and sigma-delta modulator, two filtering cascade structures composed of 5 stages comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.

Analog to digital conversion: technical aspects

An ideal radio communication receiver places the analog to digital conversion just after the antenna. It is an objective in a “software radio” perspective. The available silicon technologies do not provide the performance required by this application. We are able to evaluate the present limits and the gap between these limits and the ideal solution proposed. In this paper, we describe the present possibilities in terms of receiver architectures and we deduce theAdc specifications. Then we analyse differentAdc architectures adapted to this application. The choice is mainly between pipeline and sigma- deltaAdc. We compare them in terms of power consumption and we introduce a factor of merit. The future technologies will have an impact onAdc performance. Superconductor technology applied toAdc may be a solution and it is analysed at the end of this paper.RésuméPour la radio logicielle, la place idéale de la conversion analogique numérique est située juste après l’antenne de réception. Les technologies silicium disponibles ne permettent pas d’atteindre les performances imposées par une telle application. Nous pouvons évaluer les limites actuelles et avoir une idée du chemin qu’il reste à parcourir pour atteindre cette solution idéale. Dans cet article, nous présentons les possibilités offertes aujourd’hui par les architectures de récepteur et nous déduisons les spécifications duCan. Puis les diffé -rentes architectures de convertisseur adaptées à cette application sont analysées. Le choix doit se faire principalement entre les convertisseurs pipeline et sigma- delta. II est intéressant de les comparer en terme de puissance consommée. Connaître l’impact des technologies futures sur les performances de convertisseurs permet de montrer leur évolution dans les années à venir. La technologie des supraconducteurs appliquée à la conversion sera peut- être une solution et est envisagée à la fin de cet article.

Design and hardware implementation of digital channel selection decimating filter for multistandard receiver

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection decimating filter for multistandard receiver. Authors propose an optimized multistage decimation filter for a front-end composed by an Homodyne wide-band RF receiver and sigma-delta modulator. Design flow of hardware architecture is presented through the choice of filter structure and architecture. Several results are given to evaluate performances and complexity of designed FPGA-based implementation that can support GSM, DECT and UMTS standard.

Relaxed decimation filter specifications for wireless transceivers

This paper presents an optimized design technique for direct conversion wireless transceivers. A cascade multimode filtering structure composed of a comb filter followed by a half-band and a FIR filters is defined for both GSM and DECT standards. A practical method, which can be easily applied to any standard, is proposed to look for relaxed filter specifications in multistage structure. Good performances with low complexity architecture are obtained.

Architecture for a decoder of algebraic-geometric codes based on Hermitian curves

A new architecture is presented for hardware implementation of an algebraic-geometric code decoding algorithm based on a key equation criterion. This algorithm provides simultaneously error locator and evaluator polynomials. The architecture presented is suitable for hardware decoding of Hermitian codes.

Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections

In this paper a reconfigurable implementation for the data detection in high data rate direct sequence code division multiple access (DS-CDMA) connections is presented. Due to some well defined real time system parameters, traditional implementations of this detector which deal with the mean operational case are not optimal. They consume a lot of power in the favorable operational cases and they loose a diversity gain in the worst cases. Thanks to reconfigurability, a detector can adapt its configuration to each operational condition. Reconfigurability can perform jointly performance and computational power optimization. Implementation issues have shown that the traditional DSPs provide a high degree of flexibility but they are inefficient for the high rate processing constraints involved to DS-CDMA detection with low spreading factors (SF). A reconfigurable hardware implementation is proposed and analyzed which besides its performance capabilities provides a minimum area overhead

Optimized FPGA-based implementation of down-sampling filter for wide band radio receiver

To increase both the integration and adaptability to multiple RF communication standards, channel selection need to be performed on chip at base-band. This paper presents a low-power design and an area-efficient FPGA implementation of digital filtering cascade structure to meet multistandard radio communication specifications for a wide-band RF receiver. A filtering cascade composed of a 5th order Comb filter, a half-band filter and a FIR selector filter is proposed. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators definitions. Some experimental results are given to evaluate designed FPGA-based decimating filter circuit.

Antialiasing filtering influences on ADC specifications for radio receivers

Analog-to-digital converters (ADC) are critical components in radio receivers when channel selection is performed digitally, in direct conversion systems. Following a study on antialiasing filtering influences on sampling frequency and ADC linearity and resolution, this paper presents a way to relax ADC specifications by choosing convenient antialiasing filter specifications.