Feroze Taraporevala

Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis

A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times

A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools

A fast approach for static timing analysis covering all PVT corners

The increasing sensitivity of circuit performance to process, temperature, and supply voltage (PVT) variations has led to an increase in the number of process corners that are required to verify circuit timing. Typically, designers attempt to reduce this computational load by choosing, based on experience, a subset of the available corners and running static timing analysis (STA) at only these corners. Although running a few corners, which are chosen beforehand, can lead to acceptable results in some cases, this is not always the case. Our results show that in the case of setup timing analysis, one can indeed bound circuit slacks across all corners by running a small number of corners. On the other hand, we show that this is not possible in the case of hold analysis. Instead, we present an alternative method for performing fast and accurate hold timing analysis which covers all corners. In this method a full timing run is performed for a small number of corners, and partial timing runs, which cover only the clock network, are performed for others. We then combine the results of the full and partial runs to find the worst-case hold slacks over all corners. Our results show that this method is accurate and can achieve much improved runtimes.

A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations

Integrated circuits today rely on extensive re-use of pre-characterized IP bocks and macro cells to meet the demand for high performance system on chip (SoC). In this paper we propose a methodology for characterization of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in devices and interconnects. Increasing variability of the process parameters in sub-nanometer designs requires instance-specific characterization of these design blocks. We propose a technique for instance- specific calibration of pre-characterized timing model. The proposed approach was evaluated on large industrial designs of 1.2 M and 3.5 M gates in 65 nm technology and validated against SPICE for accuracy.